IP Library Patent Application 14837895
Patent Application
App. No. 14/837,895

ARRAY CONNECTOR AND METHOD OF MANUFACTURING THE SAME

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Quick Facts
Patent No.
US None
App. No.
14/837,895
Abstract

Array connector includes a connector body having a mating side. The connector body includes a plurality of substrate layers that are stacked side-by-side and have respective mating edges that form the mating side. The substrate layers form a plurality of interfaces in which each interface is defined between adjacent substrate layers. The adjacent substrate layers of each interface are shaped to form a plurality of channels. The array connector also includes communication lines that are disposed within corresponding channels of the connector body such that the communication lines extend along the interfaces. The communication lines are at least one of wire conductors or optical fibers. The communication lines have respective mating terminals that are positioned proximate to the mating side and form a terminal array.

Claims (29)

1 . An array connector comprising:

a connector body having a mating side, the connector body comprising a plurality of substrate layers that are stacked side-by-side and have respective mating edges that form the mating side, the substrate layers forming a plurality of interfaces in which each interface is defined between adjacent substrate layers, wherein the adjacent substrate layers form a plurality of channels therebetween; and

communication lines disposed within corresponding channels of the connector body such that the communication lines extend along the interfaces, the communication lines being wire conductors or optical fibers, the communication lines having respective mating terminals that are positioned proximate to the mating side and form a terminal array.

2 . The array connector of claim 1 , wherein the communication lines include wire conductors having end faces and the mating terminals comprise conductive bumps that are attached to the end faces of the wire conductors.

3 . The array connector of claim 2 , wherein the conductive bumps have a height of 100 μm or less and a tolerance limit that is within ±10 μm.

4 . The array connector of claim 1 , wherein the communication lines are optical fibers.

5 . The array connector of claim 1 , wherein the channels are at least one of etched channels or molded channels.

6 . The array connector of claim 1 , wherein the terminal array of mating terminals has a density of at least 50 mating terminals per 100 mm 2 .

7 . The array connector of claim 1 , wherein the mating side is a polished mating side.

8 . The array connector of claim 1 , wherein the connector body includes a body side, the communication lines extending through the body side and away from the connector body.

9 . The array connector of claim 8 , wherein at least some of the communication lines are surrounded by a common jacket.

10 . The array connector of claim 1 , further comprising a modular device, wherein the connector body is attached to the modular device to form a probe assembly, the terminal array being communicatively coupled to the modular device.

11 . A method of manufacturing an array connector comprising:

(a) forming trenches along a working layer, the working layer including a mating edge, a loading edge, and a layer side that extends therebetween, the trenches opening to the layer side and extending through the mating edge and the loading edge;

(b) disposing communication lines within the trenches thereby forming a substrate layer, the communication lines having respective mating terminals that are positioned proximate to the mating edge and extending to at least proximate to the loading edge;

(c) repeating (a) and (b) to form at least one more substrate layer; and

(d) stacking the substrate layers side-by-side, the mating edges of the substrate layers collectively forming a mating side and the mating terminals forming a terminal array.

12 . The method of claim 11 , further comprising polishing the mating side to remove segment projections of the communication lines.

13 . The method of claim 11 , wherein the communication lines include wire conductors having respective end faces, the method further comprising providing conductive bumps onto the end faces, the conductive bumps forming the mating terminals, wherein the conductive bumps are provided through at least one of solder dispensing, solder screen printing, electroplating, electrolessplating, or physical vapor deposition (PVD).

14 . The method of claim 13 , wherein the conductive bumps have a height of 100 μm or less measured from a mating surface of the mating side and a tolerance limit within ±10 μm.

15 . The method of claim 11 , wherein disposing the communication lines within the trenches includes providing an adhesive into the trenches, the adhesive securing the communication lines to the working layer.

16 . The method of claim 11 , wherein forming the trenches includes at least one of etching or molding the trenches along an SU-8 layer that is stacked onto silicon, wherein stacking the substrate layers side-by-side includes applying a silane adhesion promoter that joins the SU-8 of one substrate layer to the silicon of another substrate layer.

17 . The method of claim 11 , wherein the terminal array of mating terminals has a density of at least 50 mating terminals per 100 mm 2 .

18 . The method of claim 11 , wherein the communication lines project beyond the loading edges, the method further comprising securing the communication lines in a designated coplanar relationship, wherein securing includes at least one of positioning the communication lines parallel to one another along an adhesive surface.

19 . A method of manufacturing an array connector comprising:

(a) forming trenches along a working layer, the working layer including a mating edge, a loading edge, and opposite first and second layer sides extending therebetween, the trenches opening to the first and second layer sides and extending through the mating edge and the loading edge;

(b) disposing communication lines within the trenches thereby forming a substrate layer, the communication lines having respective mating terminals that are positioned proximate to the mating edge and extending to at least proximate to the loading edge, the mating terminals forming a terminal array; and

(c) stacking another working layer onto the first layer side of the substrate layer, the trenches of the first layer side becoming channels, wherein the other working layer is a cover layer or another substrate layer having trenches.

20 . The method of claim 19 , wherein the terminal array of mating terminals has a density of at least 50 mating terminals per 100 mm 2 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2018
From: TYCO ELECTRONICS CORPORATION
To: CREGANNA UNLIMITED COMPANY
Reel/Frame 045179/0624 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2015
From: WANG, JIAN; PETERSON, RYAN; PERALTA, FRANCES T.; PACHECO, MICHAEL PAUL; SUN, JIBIN; KHAMPHILAVONG, MALAI HONGTHONG
To: TYCO ELECTRONICS CORPORATION
Reel/Frame 036442/0212 →