Semiconductor memory device
View Patent ↗According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.
1. A semiconductor memory device comprising:
a plurality of first resistance-change memory elements of a two-terminal type;
a second resistance-change memory element of a two-terminal type;
a third resistance-change memory element of a two-terminal type;
a local bit line connected to one end of each of the first resistance-change memory elements, one end of the second resistance-change memory element and one end of the third resistance-change memory element; and
a global bit line connected to the other end of the second resistance-change memory element.
2. The device of claim 1 , wherein
the second resistance-change memory element is set to a high-resistance state by supplying a high-resistance-state setting signal between the other end of the third resistance-change memory element and the global bit line, and the second resistance-change memory element is set to a low-resistance state having a resistance lower than that in the high-resistance state by supplying a low-resistance-state setting signal between the other end of the third resistance-change memory element and the global bit line, and
data is written and read for a desired one of the first resistance-change memory elements connected to the second resistance-change memory element set to the low-resistance state.
3. The device of claim 2 , wherein
the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are stacked vertically.
4. The device of claim 3 , wherein
the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu.
5. The device of claim 2 , wherein
the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu.
6. The device of claim 1 , wherein
the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are stacked vertically.
7. The device of claim 6 , wherein
the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu.
8. The device of claim 1 , wherein
the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu.
9. The device of claim 1 , wherein
the second resistance-change memory element is connected between the local bit line and the global bit line.
10. The device of claim 1 , wherein
each of the first resistance-change memory elements is connected between the local bit line and a word line.
11. The device of claim 1 , wherein
the third resistance-change memory element is connected between the local bit line and a select switch control signal line to which a voltage for selecting the plurality of first resistance-change memory elements is applied.
12. The device of claim 1 , wherein
the global bit line is connected to a sense-amplifier and a writing driver.
13. The device of claim 1 , wherein
the second resistance-change memory element is connected between the local bit line and the global bit line,
each of the first resistance-change memory elements is connected between the local bit line and a word line,
the third resistance-change memory element is connected between the local bit line and a select switch control signal line to which a voltage for selecting the plurality of first resistance-change memory elements is applied, and
the global bit line is connected to a sense-amplifier and a writing driver.