IP Library › Granted Patent US 9,466,378

Granted Patent B2

US 9,466,378 · App. 14/842,637 · Granted Oct 11, 2016

Semiconductor memory device

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 9,466,378
App. No.: 14/842,637
Granted: Oct 11, 2016
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor memory device includes a plurality of memory cell transistors electrically connected in series, a bit line electrically connected to a first end of the memory cell transistors, a source line and a well region electrically connected to a second end of the memory cell transistors, and first and second selection transistors electrically connected in series between the second end of the memory cell transistors and the source line. During programming of a selected memory cell transistor, a first voltage is applied to the source line and the well region, and to a gate of the first selection transistor, and a second voltage smaller than the first voltage is applied to a gate of the second selection transistor.

Claims (57)

1. A semiconductor memory device comprising:

a plurality of memory cell transistors electrically connected in series;

a bit line electrically connected to a first end of the memory cell transistors;

a source line and a well region electrically connected to a second end of the memory cell transistors; and

first and second selection transistors electrically connected in series between the second end of the memory cell transistors and the source line, wherein during programming of a selected memory cell transistor,

a first voltage is applied to the source line and the well region, and to a gate of the first selection transistor, and

a second voltage smaller than the first voltage is applied to a gate of the second selection transistor.

2. The device according to claim 1 , wherein

before the first voltage is applied to the source line and the well region, the first voltage is applied to the gate of the first selection transistor and the second voltage is applied to the gate of the second selection transistor.

3. The device according to claim 1 , further comprising:

a third selection transistor electrically connected between the first end of the memory cell transistors and the bit line, wherein during the programming of the selected memory cell transistor,

a third voltage greater than the second voltage is applied to a gate of the third selection transistor.

4. The device according to claim 3 , further comprising:

a fourth selection transistor, a fifth selection transistor, a plurality of memory cell transistors, and a sixth selection transistor electrically connected in series, wherein

one end of the sixth selection transistor is electrically connected to the bit line, and one end of the fourth selection transistor is electrically connected to the source line, and

during the programming of the selected memory cell transistor, the first voltage is applied to a gate of the fourth selection transistor, and the second voltage is applied to a gate of the fifth selection transistor and a gate of the sixth selection transistor.

5. The device according to claim 3 , further comprising:

a fourth selection transistor, a fifth selection transistor, a plurality of memory cell transistors, and a sixth selection transistor electrically connected in series, wherein

one end of the sixth selection transistor is electrically connected to another bit line, and one end of the fourth selection transistor is electrically connected to the source line, and

6. The device according to claim 3 , further comprising:

a fourth selection transistor, a fifth selection transistor, a plurality of memory cell transistors, and a sixth selection transistor electrically connected in series;

a first gate line connected in common to the first and fourth selection transistors;

a second gate line connected in common to the second and fifth selection transistors; and

a third gate line connected in common to the third and sixth selection transistors, wherein

one end of the sixth selection transistor is electrically connected to another bit line, and one end of the fourth selection transistor is electrically connected to the source line and the well, and

during the programming of the selected memory cell transistor, the first voltage is applied to a gate of the fourth selection transistor through the first gate line, and the second voltage is applied to a gate of the fifth selection transistor through the second gate line.

7. The device according to claim 6 , wherein different voltages are applied to the bit lines during the programming of the selected memory cell transistor.

8. The device according to claim 3 , further comprising:

a fourth selection transistor, a fifth selection transistor, a plurality of memory cell transistors, and a sixth selection transistor electrically connected in series, wherein

one end of the sixth selection transistor is electrically connected to a bit line, and one end of the fourth selection transistor is electrically connected to the source line, and

9. The device according to claim 8 , wherein during the programming of the selected memory cell transistor, the first voltage is applied to a gate of the fifth selection transistor.

10. The device according to claim 8 , wherein during the programming of the selected memory cell transistor, the second voltage is applied to a gate of the fifth selection transistor.

11. The device according to claim 8 , wherein during the programming of the selected memory cell transistor, no voltage is applied to a gate of the fifth selection transistor so that the gate of the fifth selection transistor is in a floating state.

12. The device according to claim 3 , further comprising:

a fourth selection transistor, a fifth selection transistor, a plurality of memory cell transistors, and a sixth selection transistor electrically connected in series, wherein

one end of the sixth selection transistor is electrically connected to a bit line, and one end of the fourth selection transistor is electrically connected to the source line, and

during the programming of the selected memory cell transistor, the first voltage is applied to a gate of the fifth selection transistor, and the second voltage is applied to a gate of the sixth selection transistor.

13. The device according to claim 8 , wherein during the programming of the selected memory cell transistor, no voltage is applied to a gate of the fourth selection transistor so that the gate of the fourth selection transistor is in a floating state.

14. A semiconductor memory device comprising:

first, second, third, and fourth memory strings;

a first bit line electrically connected to first ends of the first and third memory strings;

a second bit line electrically connected to first ends of the second and fourth memory strings; and

a source line and a well region electrically connected to second ends of all the memory strings, wherein

each of the first and third memory strings includes a plurality of memory cell transistors electrically connected in series, first and second selection transistors between the memory cell transistors and the source line, and a third selection transistor between the memory cell transistors and the first bit line, and each of the second and fourth memory strings includes a plurality of memory cell transistors electrically connected in series, fourth and fifth selection transistors between the memory cell transistors and the source line, and a sixth selection transistor between the memory cell transistors and the second bit line, and

during programming of a selected memory cell transistor in the first memory string, a first voltage is applied to the source line and the well region, and also to gates of the first selection transistors and gates of the fourth selection transistors, and a second voltage smaller than the first voltage is applied to gates of the second selection transistors and gates of the fifth selection transistors.

15. The device according to claim 14 , further comprising:

a fifth memory string electrically connected between the first bit line and the source line; and

a sixth memory string electrically connected between the second bit line and the source line, wherein

each of the fifth and sixth memory strings includes a plurality of memory cell transistors electrically connected in series, seventh and eighth selection transistors between the memory cell transistors and the source line, and a ninth selection transistor between the memory cell transistors and the respective bit line, and

during the programming of the selected memory cell transistor in the first memory string, the second voltage is applied to gates of the ninth selection transistors.

16. The device according to claim 15 , wherein during the programming of the selected memory cell transistor, the first voltage is applied to gates of the seventh selection transistors.

17. The device according to claim 16 , wherein during the programming of the selected memory cell transistor, the first voltage is applied to gates of the eighth selection transistors.

18. The device according to claim 16 , wherein during the programming of the selected memory cell transistor, the second voltage is applied to gates of the eighth selection transistors.

19. The device according to claim 16 , wherein during the programming of the selected memory cell transistor, no voltage is applied to gates of the eighth selection transistors so that the gates of the eighth selection transistors are in a floating state.

20. The device according to claim 15 , wherein during the programming of the selected memory cell transistor, the first voltage is applied to gates of the eighth selection transistors, and no voltage is applied to gates of the seventh selection transistors so that the gates of the seventh selection transistors are in a floating state.

Assignments (5)

MERGER Recorded Jan 22, 2021

From: TOSHIBA MEMORY CORPORATION

To: K.K. PANGEA

Reel/Frame 055659/0471 →

CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021

From: TOSHIBA MEMORY CORPORATION

To: KIOXIA CORPORATION

Reel/Frame 055669/0001 →

CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021

From: K.K. PANGEA

To: TOSHIBA MEMORY CORPORATION