Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS)

1. A method, comprising:

in an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC):

performing in a first circuit a plurality of comparison steps; and

for each of the plurality of comparison steps, when a failure to determine a valid output decision occurs for a particular comparison step, setting in a second circuit one or more remaining bits up to, but not including, one or more overlapping redundant bits in a code word corresponding to said particular comparison step, to a particular value.

2. The method of claim 1 , further comprising setting said one or more remaining bits to a value derived from a value of a bit that was determined in an immediately preceding decision.

3. The method of claim 1 , further comprising determining that said failure occurred based on dynamic and/or adaptive criteria.

4. The method of claim 3 , wherein at least part of said criteria is selected so as to guarantee that a magnitude of a difference between an analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and an analog output digital-to-analog converter voltage is within an overlapping range of voltages corresponding to said one or more overlapping redundant bits.

5. The method of claim 1 , further comprising comparing, for said each of said plurality of comparison steps, an analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and an analog output digital-to-analog converter voltage.

6. The method of claim 5 , further comprising mapping a corresponding comparing time for said each of said plurality of comparison steps to a difference between said analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and said analog output digital-to-analog converter voltage.

7. The method of claim 6 , further comprising calibrating results from said mapping based on variations in process, temperature, and/or said analog input voltage of said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC).

8. The method of claim 5 , further comprising determining a particular value for a next bit when said corresponding comparing time for said each of said plurality of comparison steps exceeds a particular time.

9. The method of claim 8 , wherein a particular time indicates that a magnitude of a difference between said analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and said analog output digital-to-analog converter voltage is less than a fractional portion of a current step size of a digital-to-analog converter (DAC) that generates said analog output digital-to-analog converter voltage.

10. The method of claim 9 , wherein said fractional portion comprises ½, ¼, ⅛, 1/16 and/or 1/32.

11. A system, comprising:

an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that comprises:

a comparator circuit operable to perform one or more comparison steps; and

a control circuit operable to, when a failure to determine a valid output decision for a particular comparison step occurs, set one or more remaining bits up to, but not including, one or more overlapping redundant bits in a code word corresponding to said particular comparison step, to a particular value.

12. The system of claim 11 , wherein said control circuit is operable to set said one or more remaining bits to a value derived from a value of a bit that was determined in an immediately preceding decision.

13. The system of claim 11 , wherein said control circuit is operable to determine that said failure occurred based on dynamic and/or adaptive criteria.

14. The system of claim 13 , wherein at least part of said criteria is selected so as to guarantee that a magnitude of a difference between an analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and an analog output digital-to-analog converter voltage is within an overlapping range of voltages corresponding to said one or more overlapping redundant bits.

15. The system of claim 11 , wherein said comparator circuit is operable to compare an analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and an analog output digital-to-analog converter voltage.

16. The system of claim 15 , wherein said control circuit is operable to map a corresponding comparing time to a difference between said analog input voltage to said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) and said analog output digital-to-analog converter voltage.

17. The system of claim 16 , wherein said control circuit is operable to calibrate results from said mapping based on variations in process, temperature, and/or said analog input voltage of said asynchronous successive approximation register (SAR) analog-to-digital converter (ADC).

18. The system of claim 15 , wherein said control circuit is operable to determine a particular value for a next bit when said corresponding comparing time exceeds a particular time.

19. The system of claim 18 , further comprising a digital-to-analog converter (DAC) operable to generate said analog output digital-to-analog converter voltage, wherein said exceeding of said a particular time indicates that a magnitude of a difference between said analog input voltage to said SAR ADC and said analog output digital-to-analog converter voltage is less than a fractional portion of a current step size of said DAC.

20. The system of claim 19 , wherein said fractional portion comprises ½, ¼, ⅛, 1/16 and/or 1/32.