Granted Patent B1

US 9,431,051 · App. 14/844,864 · Granted Aug 30, 2016

Abstract

Claims (57)

1. A data processing system, the system comprising:

an analog to digital converter circuit operable to convert an analog input into a series of digital samples, wherein the series of digital samples includes a preamble pattern;

an amplitude estimation circuit operable to estimate an amplitude of the series of digital samples corresponding to the preamble pattern received during acquisition phase processing;

a comparator circuit operable to compare the amplitude with a window threshold;

an acquisition gain feedback calculation circuit operable to calculate a gain correction based at least in part on a result of comparing the amplitude with the window threshold; and

a data correction circuit operable to correct the digital samples corresponding to the preamble pattern by an amount corresponding to the gain correction.

2. The data processing system of claim 1 , wherein the window threshold is a first window threshold, wherein the result is a first result, wherein the comparator is a first comparator circuit, the system further comprising:

a second comparator circuit operable to compare the amplitude with a second window threshold to yield a second result; and

wherein the gain calculation circuit is operable to calculate the gain correction based at least in part on the first result and the second result.

3. The data processing system of claim 2 , wherein the acquisition gain feedback calculation circuit is operable to:

apply a first correction algorithm to correct the digital samples corresponding to the preamble pattern when the amplitude is outside the second window threshold and within the first window threshold; and

apply a second correction algorithm to correct the digital samples corresponding to the preamble pattern when the amplitude is outside both the second window threshold and the first window threshold.

4. The data processing system of claim 3 , wherein the first correction algorithm includes multiplying a buffered version of the series of digital samples by an overall gain offset.

5. The data processing system of claim 4 , wherein the second correction algorithm includes incrementally multiplying on a period by period basis the buffered version of the series of digital samples by a period gain, wherein the period gain is the overall gain offset divided by a number of bit periods, and wherein the number of bit periods is greater than two.

6. The data processing system of claim 2 , wherein the analog input is a first analog input, and wherein the system further comprises:

a variable gain amplifier circuit operable to amplify a second analog input by a variable gain corresponding to a gain feedback value to yield an amplified output, wherein the first analog input is derived from the amplified output; and

wherein the acquisition gain feedback calculation circuit is operable to leave the gain feedback value unchanged when the amplitude is within the first window threshold.

7. The data processing system of claim 2 , wherein the analog input is a first analog input, and wherein the system further comprises:

a variable gain amplifier circuit operable to amplify a second analog input by a variable gain corresponding to a gain feedback value to yield an amplified output, wherein the first analog input is derived from the amplified output; and

wherein the acquisition gain feedback calculation circuit is operable to modify the gain feedback value when the amplitude is outside the first window threshold.

8. The data processing system of claim 1 , wherein the system is implemented as part of an integrated circuit.

9. The data processing system of claim 1 , wherein the system is implemented as part of a storage device, and wherein the storage device further comprises:

the storage medium, wherein the analog input is derived from a read head disposed over a track on the storage medium.

10. The data processing system of claim 1 , wherein the amplitude estimation circuit is a zero gain start circuit.

11. A method for modifying a gain feedback value, the method comprising:

receiving a first portion of data derived from a storage medium during a tracking phase;

receiving a second portion of data derived from the storage medium during an acquisition phase;

applying a first variable gain amplification to the first portion of data to yield a first amplified output, wherein the variable gain amplification is governed at least in part by a first gain feedback generated based upon the first portion of data;

converting a first analog input corresponding to the first amplified output to a first series of digital samples;

applying a second variable gain amplification to the second portion of data to yield a second amplified output, wherein the second variable gain amplification is governed at least in part by a second gain feedback;

converting a second analog input corresponding to the second amplified output to a second series of digital samples;

using an acquisition phase gain modification circuit to: estimate an amplitude of the second series of digital samples to yield an amplitude, and calculate a gain correction based at least in part on the amplitude; and

correcting the second series of digital samples using the gain correction to yield corrected samples.

12. The method of claim 11 , wherein the method further comprises:

using the acquisition phase gain modification circuit to: compare the amplitude with a first window threshold to yield a first result, and compare the amplitude with a second window threshold to yield a second result; and

wherein calculating the gain correction is based at least in part on a result of comparing the amplitude with the window threshold.

13. The method of claim 12 , wherein the second gain feedback is left unchanged when the amplitude is within the first window threshold.

14. The method of claim 12 , wherein the second gain feedback is modified when the amplitude is outside the first window threshold.

15. The method of claim 12 , the method further comprising:

using the acquisition phase gain modification circuit to:

apply a first correction algorithm to correct the second series of digital samples when the amplitude is outside the second window threshold and within the first window threshold; and

apply a second correction algorithm to correct the second series of digital samples when the amplitude is outside both the second window threshold and the first window threshold.

16. The method of claim 15 , the method further comprising:

calculating an overall gain offset as a difference between the amplitude and an expected amplitude.

17. The method of claim 16 , wherein the first correction algorithm includes multiplying a buffered version of the second series of digital samples by the overall gain offset.

18. The method of claim 16 , the method further comprising:

calculating a period gain by dividing the overall gain offset by a number of bit periods, wherein the number of bit periods is greater than two.

19. The method of claim 18 , wherein the second correction algorithm includes incrementally multiplying on a period by period basis the buffered version of the second series of digital samples by the period gain.

20. A storage device, the storage device comprising:

a head including a read sensor disposable over a storage medium and operable to sense information on the storage medium and provide a corresponding sensed signal;

a variable gain amplifier circuit operable to amplify an input signal derived from the sensed signal by a variable gain corresponding to a gain feedback value to yield an amplified output;

an analog to digital converter circuit operable to convert an analog input into a series of digital samples, wherein the series of digital samples includes a preamble pattern, and wherein the analog input is derived from the amplified output;

an amplitude estimation circuit operable to estimate an amplitude of the series of digital samples corresponding to the preamble pattern received during acquisition phase processing;

a first comparator circuit operable to compare the amplitude with a first window threshold to yield a first result;

a second comparator circuit operable to compare the amplitude with a second window threshold to yield a second result;

an acquisition gain feedback calculation circuit operable to calculate a gain correction based at least in part on the first result and the second result, wherein the acquisition gain feedback calculation circuit is operable to leave the gain feedback value unchanged when the amplitude is within the first window threshold, and to modify the gain feedback value when the amplitude is outside the first window threshold; and

a data correction circuit operable to correct the digital samples corresponding to the preamble pattern by an amount corresponding to the gain correction.

Assignments (8)