Power semiconductor devices
View Patent ↗A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate. The diode part includes a p-type body region disposed inside the substrate and electrically connected with the anode terminal, an n-type well disposed on one side of the p-type body region and having a first impurity concentration, and a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration which is lower than the first impurity concentration.
1. A power semiconductor device, comprising:
a diode part disposed in a first region of a substrate;
a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate;
an anode terminal disposed on the first region of the substrate; and
a cathode terminal disposed on the second region of the substrate,
the diode part including:
a p-type body region disposed inside the substrate and having an upper portion connected with the anode terminal,
an n-type well disposed on one side of the p-type body region, and having a first impurity concentration, the n-type well having an upper portion of a sidewall surrounding the p-type body region, and
a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration lower than the first impurity concentration, the n-type well having a lower portion of the sidewall surrounding the first n-type semiconductor region; and
the JFET part including:
a second n-type semiconductor region disposed above a p-type base substrate, and
an n-type buried layer aligned along an interface between the second n-type semiconductor region and the p-type base substrate.
2. The power semiconductor device of claim 1 , wherein a bottom of the p-type body region is positioned at a higher level than a bottom of the n-type well.
3. The power semiconductor device of claim 1 , further comprising a lower barrier region formed below the first n-type semiconductor region and the n-type well in the first region of the substrate.
4. The power semiconductor device of claim 3 , wherein a bottom of the n-type well is in contact with a top of the lower barrier region.
5. The power semiconductor device of claim 3 , wherein the first n-type semiconductor region is in contact with a top of the lower barrier region.
6. The power semiconductor device of claim 3 , wherein a bottom of the p-type body region is not in contact with a top of the lower barrier region.
7. The power semiconductor device of claim 1 , wherein the p-type body region and the first n-type semiconductor region overlap each other in a direction perpendicular to an upper surface of the substrate.
8. The power semiconductor device of claim 1 , wherein the p-type body region and the first n-type semiconductor region define a p-n junction diode.
9. A power semiconductor device comprising:
a diode part disposed in a first region of a substrate;
a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate;
an anode terminal disposed on the first region of the substrate; and
a cathode terminal disposed on the second region of the substrate,
the diode part including:
a p-type body region disposed inside the substrate and haying an upper portion connected with the anode terminal,
an n-type well disposed on one side of the p-type body region, and having a first impurity concentration,
a lateral p-type well disposed on one side of the n-type well in the first region of the substrate,
a lateral n-type well disposed on one side of the lateral p-type well such that the lateral p-type well is positioned between the lateral n-type well and the n-type well,
a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration lower than the first impurity concentration, and
a lower barrier region disposed below and in contact with the lateral n-type well: and
the JFET part including:
a second n-type semiconductor region disposed above a p-type base substrate, and
an n-type buried layer aligned along an interface between the second n-type semiconductor region and the p-type base substrate.
10. The power semiconductor device of claim 9 , wherein JFET part further includes a p-type field forming layer disposed on the n-type semiconductor region, the n-type buried layer has at least one part overlapping the p-type field forming layer in a direction perpendicular to an upper surface of the substrate.
11. A power semiconductor device, comprising:
a diode part disposed in a first region of a substrate;
a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate;
an anode terminal disposed on the first region of the substrate; and
a cathode terminal disposed on the second region of the substrate,
the JFET part including:
an n-type semiconductor region disposed above a p-type base substrate,
a p-type field forming layer disposed on the n-type semiconductor region,
an entirety of the p-type field forming layer being disposed lateral to a contact of the cathode terminal with the second region of the substrate, and
an n-type buried layer disposed at an interface between the n-type semiconductor region and the p-type base substrate, the n-type buried layer having at least one part overlapping the p-type field forming layer in a direction perpendicular to an upper surface of the substrate.
12. The power semiconductor device of claim 11 , wherein the n-type buried layer overlaps the cathode terminal in a direction perpendicular to an upper surface of the substrate.
13. The power semiconductor device of claim 11 , wherein:
the n-type semiconductor region has a first impurity concentration; and
the n-type buried layer has a second impurity concentration greater than the first impurity concentration.
14. The power semiconductor device of claim 13 , further comprising an n-type lower layer disposed adjacent to the n-type buried layer below the cathode terminal,
wherein the n-type lower layer has a third impurity concentration greater than the second impurity concentration of the n-type buried layer.
15. A power semiconductor device, comprising:
a base substrate including a semiconductor material;
a semiconductor material layer disposed on the base substrate and including a first region and a second region;
a diode part disposed in the first region of the semiconductor material layer, the diode part including:
a p-type body region disposed in an upper portion of the semiconductor material layer,
an n-type well disposed on one side of the p-type body region, and
a first n-type semiconductor region disposed below the p-type body region and having a first impurity concentration; and
a junction field effect transistor (JFET) part disposed in the second region of the semiconductor material layer, the JFET part including:
a p-type field forming layer disposed in an upper portion of the semiconductor material layer,
a second n-type semiconductor region disposed between the p-type field forming layer and a p-type base substrate, the second n-type semiconductor region having a second impurity concentration,
a p-type well region including a gate region, the p-type well region being in contact with one side of the p-type field forming layer, and
an n-type buried layer having a first portion disposed above an interface between the second n-type semiconductor region and the p-type base substrate, the n-type buried layer having second portion disposed below the interface, the n-type buried layer having at least one part overlapping the p-type field forming layer in a direction perpendicular to an upper surface of the base substrate
the first impurity concentration and the second impurity concentration being the same.
16. The power semiconductor device of claim 15 , further comprising:
an anode terminal disposed on the first region of the semiconductor material layer and electrically connected with the p-type body region; and
a cathode terminal disposed on the second region of the semiconductor layer and electrically connected with the second n-type semiconductor region.
17. The power semiconductor device of claim 15 , further comprising:
a lower barrier region disposed below the first n-type semiconductor region and the n-type well, inside the base substrate; and
an n-type buried layer disposed below the second n-type semiconductor region, inside the base substrate.
18. The power semiconductor device of claim 17 , wherein the n-type buried layer has a third impurity concentration greater than the second impurity concentration.
19. The power semiconductor device of claim 15 , wherein:
the semiconductor material layer includes a silicon epitaxial layer including an n-type impurity; and
the first n-type semiconductor region and the second n-type semiconductor region are portions of the silicon epitaxial layer.