IP Library Patent Application 14845961
Patent Application
App. No. 14/845,961

METHOD AND SYSTEM FOR A MULTI-LEVEL ENCODED DATA PATH WITH DECODER

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Quick Facts
Patent No.
US None
App. No.
14/845,961
Abstract

Methods and systems for a multi-level encoded data path with decoder are disclosed and may include, in a receiver on a chip: receiving a multi-level encoded signal, generating a plurality of copy signals offset from the multi-level encoded signal by a configurable offset voltage, comparing each copy signal against a different threshold level, and generating binary data based on the comparison. At least one of the plurality of copy signals may be compared using a clock data recovery module and/or using a retimer, which may comprise at least one D flip-flop. The multi-level encoded signal may comprise a pulse amplitude modulated-4 (PAM-4) signal. The multi-level encoded signal may be received from a photodiode on the chip. An optical signal may be communicated to the photodiode from a grating coupler on the chip.

Claims (35)

1 . A method for communication, the method comprising:

in a receiver on a chip:

receiving a multi-level encoded signal;

generating a plurality of copy signals offset from the multi-level encoded signal by a configurable offset voltage;

comparing each copy signal against a different threshold level; and

generating binary data based on the comparing of each copy signal.

2 . The method according to claim 1 , comprising comparing at least one of the plurality of copy signals using a clock data recovery module.

3 . The method according to claim 1 , comprising comparing at least one of the plurality of copy signals using a retimer.

4 . The method according to claim 3 , wherein the retimer comprises at least one D flip-flop.

5 . The method according to claim 1 , wherein the multi-level encoded signal comprises a pulse amplitude modulated (PAM) signal.

6 . The method according to claim 5 , wherein the PAM signal comprises a PAM-4 signal.

7 . The method according to claim 1 , comprising receiving the multi-level encoded signal from a photodiode on the chip.

8 . The method according to claim 8 , comprising communicating an optical signal to the photodiode from a grating coupler on the chip.

9 . The method according to claim 1 , comprising generating offset voltages for said plurality of copy signals using a level shifter comprising parallel transistor/resistor current mirror branches.

10 . The method according to claim 1 , wherein the semiconductor die comprises a silicon complementary-metal oxide semiconductor (CMOS) photonics die.

11 . A system for communication, the system comprising:

a receiver on a chip, the receiver being operable to:

receive a multi-level encoded signal;

generate a plurality of copy signals offset from the multi-level encoded signal by a configurable offset voltage;

compare each copy signal against a different threshold level; and

generate binary data based on the comparing of each copy signal.

12 . The system according to claim 11 , wherein the receiver is operable to compare at least one of the plurality of copy signals using a clock data recovery module.

13 . The system according to claim 11 , wherein the receiver is operable to compare at least one of the plurality of copy signals using a retimer.

14 . The system according to claim 13 , wherein the retimer comprises at least one D flip-flop.

15 . The system according to claim 11 , wherein the multi-level encoded signal comprises a pulse amplitude modulated (PAM) signal.

16 . The system according to claim 15 , wherein the PAM signal comprises a PAM-4 signal.

17 . The system according to claim 11 , wherein the receiver is operable to receive the multi-level encoded signal from a photodiode on the chip.

18 . The system according to claim 11 , wherein the receiver is operable to communicate an optical signal to the photodiode from a grating coupler on the chip.

19 . The system according to claim 11 , wherein the receiver is operable to generate offset voltages for said plurality of copy signals using a level shifter comprising parallel transistor/resistor current mirror branches.

20 . A system for communication, the system comprising:

a receiver on a chip, the receiver being operable to:

receive a pulse amplitude modulated-4 (PAM-4) encoded signal;

generate two copy signals offset from the multi-level encoded signal by a configurable offset voltage;

compare each copy signal against a different threshold level; and

generate binary data based on the comparing of each copy signal.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2023
From: WELCH, BRIAN
To: LUXTERA INC.
Reel/Frame 063406/0417 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →