PARASITIC CHANNEL MITIGATION VIA IMPLANTATION OF LOW ATOMIC MASS SPECIES
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
1 . A method of forming a semiconductor structure, comprising:
implanting a species having a relative atomic mass of less than 5 into a substrate comprising silicon to produce a surface region comprising no parasitic channel or comprising a low-conductivity parasitic channel wherein, during the implanting step, at least a portion of the species is implanted through a III-nitride material region.
2 . The method of claim 1 , wherein the III-nitride material region is an epitaxial III-nitride material region.
3 . The method of claim 1 , comprising, after the implanting step, forming a second III-nitride material region over the III-nitride material region.
4 . The method of claim 3 , wherein the second III-nitride material region is an epitaxial III-nitride material region.
5 . (canceled)
6 . The method of claim 1 , wherein the substrate comprises at least a layer having a resistivity of greater than about 10 2 Ohms-cm.
7 . The method of claim 1 , wherein the substrate is a silicon substrate.
8 . The method of claim 7 , wherein the substrate is a bulk silicon wafer.
9 . The method of claim 7 , wherein the substrate is a silicon-on-insulator substrate.
10 . The method of claim 1 , wherein the substrate is a silicon carbide substrate.
11 . The method of claim 1 , wherein the III-nitride material region comprises GaN.
12 . The method of claim 1 , wherein the species having a relative atomic mass of less than 5 comprises hydrogen and/or helium.
13 - 15 . (canceled)
16 . The method of claim 3 , wherein the second III-nitride material region comprises a 2DEG.
17 . The method of claim 1 , wherein the semiconductor structure comprises a transistor located over the surface region of the substrate.
18 . (canceled)
19 . The method of claim 1 , wherein implanting the species having a relative atomic mass of less than 5 into the substrate produces a surface region comprising a low-conductivity parasitic channel.
20 . The method of claim 19 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 .
21 . The method of claim 19 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 .
22 - 29 . (canceled)
30 . The method of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
31 . The method of claim 1 , wherein a diffusion barrier region is located between the III-nitride material region and the substrate.
32 - 33 . (canceled)
34 . The method of claim 1 , wherein, before the implanting step, the substrate comprises a surface region comprising a high-conductivity parasitic channel.
35 - 38 . (canceled)