PARASITIC CHANNEL MITIGATION VIA COUNTERDOPANT PROFILE MATCHING
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
1 . A semiconductor structure, comprising:
a substrate comprising silicon; and
a III-nitride material region located over a surface region of the substrate, wherein:
the substrate comprises at least one p-type dopant defining a p-type dopant concentration profile, and
the substrate comprises at least one n-type dopant defining a n-type dopant concentration profile that is substantially matched to the p-type dopant concentration profile.
2 . The semiconductor structure of claim 1 , wherein the at least one p-type dopant comprises Ga, In, and/or Al.
3 . The semiconductor structure of claim 1 , wherein the at least one n-type dopant comprises As and/or P.
4 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Group III species in the substrate is at least about 10 17 /cm 3 .
5 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Al, Ga, and In in the substrate is at least about 10 17 /cm 3 .
6 . The semiconductor structure of claim 1 , wherein the peak concentration of Al, Ga, and/or In in the substrate is at least about 10 17 /cm 3 .
7 . A method of forming a semiconductor structure, comprising:
implanting a counter-dopant into a semiconductor structure comprising a III-nitride material region and a substrate comprising silicon such that a concentration profile of the counter-dopant substantially matches a concentration profile of a second dopant present within the substrate.
8 - 19 . (canceled)
20 . The semiconductor structure of claim 1 , wherein the substrate comprises at least a layer having a resistivity of greater than about 10 2 Ohms-cm.
21 . The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate.
22 . The semiconductor structure or method of claim 1 , wherein the substrate is a bulk silicon wafer.
23 . The semiconductor structure of claim 1 , wherein the substrate is a silicon-on-insulator substrate.
24 . The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate.
25 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN.
26 . The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate.
27 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride nucleation layer.
28 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride transition layer.
29 . The semiconductor structure of claim 28 , wherein the III-nitride transition layer is compositionally graded.
30 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride buffer layer.
31 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
32 - 34 . (canceled)
35 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a 2 DEG.