PARASITIC CHANNEL MITIGATION USING ALUMINUM NITRIDE DIFFUSION BARRIER REGIONS
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
1 . A semiconductor structure, comprising:
a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm;
a low-temperature AlN region located over the substrate;
a high-temperature AlN region located over the substrate; and
a III-nitride material region located over the low-temperature AlN region and over the high-temperature AlN region.
2 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Group III species in the substrate is less than about 10 17 /cm 3 .
3 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm.
4 . The semiconductor structure of claim 1 , wherein the peak concentration of Al, Ga, and/or In in the substrate is less than about 10 17 /cm 3 .
5 . The semiconductor structure of claim 1 , wherein the low-temperature AlN region is over the high-temperature AlN region.
6 . The semiconductor structure of claim 1 , wherein the high-temperature AlN region is over the low-temperature AlN region.
7 . A method of forming a semiconductor structure, comprising:
forming a first AlN region over a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm, wherein the temperature of the environment in which the first AlN region is formed is between about 700° C. and about 950° C.;
forming a second AlN region over the substrate, wherein the temperature of the environment in which the second AlN region is formed is from about 950° C. to about 1150° C.; and
forming a III-nitride material region over the first AlN region and over the second AlN region.
8 . The method of claim 7 , wherein the second AlN region is formed over the first AlN region.
9 . The method of claim 7 , wherein the first AlN region is formed over the second AlN region.
10 . The method of claim 7 , wherein, after the III-nitride material is formed, the peak of the sum of the concentrations of Group III species in the substrate is less than about 10 17 /cm 3 .
11 . The method of claim 7 , wherein, after the III-nitride material is formed, the peak of the sum of the concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm.
12 . The method of claim 7 , wherein, after the III-nitride material is formed, the peak concentration of Al, Ga, and/or In in the substrate is less than about 10 17 /cm 3 .
13 . The semiconductor structure of claim 1 , wherein the substrate comprises at least a layer having a resistivity of greater than about 10 2 Ohms-cm.
14 . The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate.
15 . The semiconductor structure of claim 14 , wherein the substrate is a bulk silicon wafer.
16 . The semiconductor structure of claim 14 , wherein the substrate is a silicon-on-insulator substrate.
17 . The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate.
18 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN.
19 . The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate.
20 - 22 . (canceled)
23 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
24 - 26 . (canceled)