PARASITIC CHANNEL MITIGATION USING SILICON CARBIDE DIFFUSION BARRIER REGIONS
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
1 . A semiconductor structure, comprising:
a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm;
a diffusion barrier region comprising silicon carbide located over a surface of the substrate; and
a III-nitride material region located over the diffusion barrier region comprising silicon carbide.
2 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Group III species in the substrate is less than about 10 17 /cm 3 .
3 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm.
4 . The semiconductor structure of claim 1 , wherein the peak concentration of Al, Ga, and/or In in the substrate is less than about 10 17 /cm 3 .
5 . The semiconductor structure of claim 1 , wherein the substrate comprises a surface region associated with the surface of the substrate, and the surface region comprises a low-conductivity parasitic channel or the substrate is free of a parasitic channel.
6 . The semiconductor structure of claim 5 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 .
7 . The semiconductor structure of claim 5 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 .
8 . A method of forming a semiconductor structure, comprising:
forming a diffusion barrier region comprising silicon carbide over a substrate comprising silicon, the substrate comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; and
forming a III-nitride material region over the diffusion barrier region comprising silicon carbide.
9 - 15 . (canceled)
16 . The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate.
17 . The semiconductor structure of claim 16 , wherein the substrate is a bulk silicon wafer.
18 . The semiconductor structure of claim 16 , wherein the substrate is a silicon-on-insulator substrate.
19 . The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate.
20 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN.
21 . The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate.
22 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride nucleation layer.
23 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride transition layer.
24 . The semiconductor structure of claim 23 , wherein the III-nitride transition layer is compositionally graded.
25 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride buffer layer.
26 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
27 - 29 . (canceled)