High-linearity CMOS WiFi RF power amplifiers in wide range of burst signals
An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.
1. A radio frequency (RF) power amplifier circuit, comprising:
a power amplifier including a power amplifier output and an RF signal input;
a control circuit selectively biasing the power amplifier, the control circuit including:
an auxiliary current source;
a ramp-up capacitor connected to the auxiliary current source;
a ramp-up switch connected to the auxiliary current source, the ramp up switch selectively activating the auxiliary current source and charging the ramp-up capacitor in response to a control signal corresponding to an RF signal burst;
a buffer including an output and an input connected to the ramp-up capacitor, voltage at the input of the buffer being linearly dependent over an RF signal burst duration; and
a main current source connected to the output of the buffer at a sum node connected to the power amplifier, the main current source generating a constant current during the RF signal burst.
2. The RF power amplifier circuit of claim 1 further comprising:
an RF decoupling resistor; and
a mirror transistor biased by the main current source and connected to the power amplifier, the power amplifier including a power amplifier transistor connected to the mirror transistor over the RF decoupling resistor.
3. The RF power amplifier circuit of claim 2 wherein:
the power amplifier transistor and the mirror transistor each include a gate terminal, a drain terminal, and a source terminal;
the gate terminal of the power amplifier transistor is connected to the RF signal input and a first terminal of the RF decoupling resistor; and
the gate terminal of the mirror transistor is connected to a second terminal of the RF decoupling resistor and to the drain terminal of the mirror transistor.
4. The RF power amplifier circuit of claim 3 wherein the buffer includes a buffer transistor with a gate terminal connected to the ramp-up capacitor and a source terminal connected to the drain terminal of the mirror transistor.
5. The RF power amplifier circuit of claim 1 wherein the ramp-up switch is a transistor with a gate terminal connected to a start ramp signal input, and a drain terminal connected to the auxiliary current source.
6. The RF power amplifier circuit of claim 1 wherein the control circuit further includes a ramp-down switch connected to the ramp-up capacitor that is selectively activated at an end of the RF signal burst to discharge the ramp-up capacitor, the ramp-up switch being deactivated at the end of the RF signal burst.
7. The RF power amplifier circuit of claim 6 wherein the ramp-down switch is a transistor with a gate terminal connected to a stop ramp signal input, and a drain terminal connected to the input of the buffer and the ramp-up capacitor.
8. The RF power amplifier circuit of claim 1 wherein the input of the buffer is directly connected to the ramp-up capacitor.
9. The RF power amplifier circuit of claim 1 further comprising:
a capacitor discharge resistor connected to the ramp-up capacitor; and
an inverter including an input connected to the ramp-up capacitor and an output connected to the buffer, voltage at the input of the inverter exponentially decaying in a duration less than a minimum RF signal burst duration.
10. The RF power amplifier circuit of claim 9 wherein values of the ramp-up capacitor and the capacitor discharge resistor correspond to a specific exponential decay of the voltage at the input of the inverter.
11. An RF power amplifier biasing circuit with a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output, the RF power amplifier biasing circuit comprising:
a ramp-up capacitor connected to the auxiliary current source input;
a ramp-up switch transistor connected to the start ramp signal input, the ramp-up switch transistor being selectively activated thereby to connect the auxiliary current source input to the ramp-up capacitor;
a buffer stage with an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node; and
a mirror transistor with a gate terminal corresponding to the circuit output and a drain terminal connected to the sum node and to the gate terminal.
12. The RF power amplifier biasing circuit of claim 11 further comprising an RF signal decoupling resistor connected to the gate terminal of the mirror transistor.
13. The RF power amplifier biasing circuit of claim 11 wherein the buffer stage includes a buffer transistor with a gate terminal connected to the ramp-up capacitor and a source terminal connected to the sum node.
14. The RF power amplifier biasing circuit of claim 11 further comprising a ramp-down switch transistor with a gate terminal connected to a stop ramp signal input and a drain terminal connected to the ramp-up capacitor.
15. The RF power amplifier biasing circuit of claim 11 further comprising:
an inverter stage with an input connected to the ramp-up capacitor and an output connected to the input of the buffer stage; and
a capacitor discharge resistor connected to the ramp-up capacitor.
16. The RF power amplifier biasing circuit of claim 11 wherein the ramp-up switch transistor is selectively activated by a pulse signal on the start ramp signal input.
17. The RF power amplifier circuit of claim 11 wherein the buffer stage includes a buffer transistor with a gate terminal connected to the ramp-up capacitor and a source terminal connected to the drain terminal of the mirror transistor.
18. The RF power amplifier circuit of claim 11 further comprising a ramp-down switch connected to the ramp-up capacitor that is selectively activated at an end of the RF signal burst to discharge the ramp-up capacitor, the ramp-up switch being deactivated at the end of the RF signal burst.
19. The RF power amplifier circuit of claim 18 wherein the ramp-down switch is a transistor with a gate terminal connected to a stop ramp signal input, and a drain terminal connected to the input of the buffer stage and the ramp-up capacitor.
20. The RF power amplifier circuit of claim 15 wherein values of the ramp-up capacitor and the capacitor discharge resistor correspond to a specific exponential decay of the voltage at the input of the inverter stage.
21. An RF power amplifier biasing circuit with a biasing output and connectable to a band gap reference circuit with a first current output generating a first voltage level and a second current output generating a second voltage level, the circuit comprising:
a switch having a first throw terminal connected to the first current output of the band gap reference circuit, a second throw terminal connected to the second current output of the band gap reference circuit, and a pole terminal, the switch selectively connecting the first throw terminal and the second throw terminal to the pole terminal in response to a switch enable input;
an operational amplifier with a first differential input, a second differential input, and an operational amplifier output, the operational amplifier being powered by the band gap reference circuit;
a ramping resistor-capacitor network connected to the first differential input of the operational amplifier, a ramping resistor of the ramping resistor-capacitor network being connected to the pole terminal of the switch;
an output transistor connected to the output of the operational amplifier and having an output defining the biasing output; and
a feedback resistor network connected to the output transistor and to the second differential input of the operational amplifier;
wherein a voltage on the biasing output ramps from the first voltage level to the second voltage level in conjunction with the switch being selectively activated from connecting the first throw terminal and the pole terminal, to connecting the second throw terminal and the pole terminal.
22. The RF power amplifier biasing circuit of claim 21 wherein the ramping resistor-capacitor network defines a time constant for ramping the voltage on the biasing output from the first voltage level to the second voltage level.
23. The RF power amplifier biasing circuit of claim 21 wherein the output transistor is a PMOS type defined by a gate, a source, and a drain, the gate being connected to the output of the operational amplifier, the source being connected to the band gap reference circuit, and the drain being connected to the biasing output and the feedback resistor network.
24. The RF power amplifier biasing circuit of claim 21 wherein the feedback resistor network is a voltage divider circuit including a first resistor and a second resistor.
25. The RF power amplifier biasing circuit of claim 24 wherein:
the first resistor is connected to the output transistor and the second differential input of the operational amplifier; and
the second resistor is connected to the first resistor and the second differential input of the operational amplifier.
26. The RF power amplifier biasing circuit of claim 21 wherein the first voltage level on the first current output of the band gap reference circuit and the second voltage level on the second current output of the band gap reference circuit are adjustable in response to measured ambient temperature.