IP Library Patent Application 14851295
Patent Application
App. No. 14/851,295

METHOD AND CIRCUIT FOR ELIMINATING TRANSFORMER SATURATION IN THE PRESENCE OF DC OFFSET VOLTAGE

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Quick Facts
Patent No.
US None
App. No.
14/851,295
Abstract

A DC offset voltage in an AC input voltage to a transformer and associated saturation current are eliminated by the placement of an anti-parallel diode pair circuit in series between a source of the AC input voltage and a primary winding of the transformer. The anti-parallel diode pair circuit has an input coupled to an output by parallel connected oppositely biased branch diode circuits. Each branch diode circuit has at least one diode where the diode of one such branch diode circuit is biased in one direction and the diode of the other such branch diode circuit is biased in an opposite direction and each branch diode circuit has the same number of diodes as the other branch diode circuit.

Claims (15)

1 . A method of eliminating a DC offset voltage in an AC input voltage to a transformer and associated saturation current of the transformer, comprising:

placing an anti-parallel diode pair circuit in series between a source of the AC input voltage and a primary winding of the transformer.

2 . The method of claim 1 wherein placing the anti-parallel diode pair circuit includes placing an anti-parallel diode pair circuit having parallel connected oppositely biased branch diode circuits with each branch diode circuit having at least one diode where the diode of one such branch diode circuit is biased in one direction and the diode of the other such branch diode circuit is biased in an opposite direction and each branch diode circuit has the same number of diodes as the other branch diode circuit.

3 . The method of claim 2 wherein placing as the anti-parallel diode pair circuit includes placing an anti-parallel diode pair circuit having parallel connected oppositely biased branch diode circuit where each branch diode circuit includes two diodes connected in series with each other with the diodes of one of the branch diode circuits biased in the one direction and the diodes of the other branch diode circuits biased in the opposite direction.

4 . The method of claim 3 wherein placing as the anti-parallel diode pair circuit includes placing an anti-parallel diode pair circuit having midpoints of the branch diode circuits connected together.

5 . An anti-parallel diode pair circuit, comprising:

an input coupled to an output by parallel connected branch diode circuits; and

each branch diode circuit having at least one diode where the diode of one such branch diode circuit is biased in one direction and the diode of the other such branch diode circuit is biased in an opposite direction and each branch diode circuit has the same number of diodes as the other branch diode circuit.

6 . The anti-parallel diode pair circuit of claim 5 , wherein each branch diode circuit includes two diodes connected in series with each other with the diodes of one of the branch diode circuits biased in the one direction and the diodes of the other branch diode circuits biased in the opposite direction.

7 . The anti-parallel diode pair circuit of claim 6 wherein midpoints of the branch diode circuits are connected together.

8 . In combination, a transformer and anti-parallel diode pair circuit, comprising:

the anti-parallel diode pair circuit coupled in series between a primary winding of the transformer and a source of an AC input voltage to the transformer.

9 . The combination of claim 8 wherein the anti-parallel diode pair circuit includes an input coupled to an output by parallel connected branch diode circuits and each branch diode circuit having at least one diode where the diode of one such branch diode circuit is biased in one direction and the diode of the other such branch diode circuit is biased in an opposite direction and each branch diode circuit has the same number of diodes as the other branch diode circuit.

10 . The combination of claim 9 wherein each branch diode circuit includes two diodes connected in series with each other with the diodes of one of the branch diode circuits biased in the one direction and the diodes of the other branch diode circuits biased in the opposite direction.

11 . The combination of claim 10 wherein midpoints of the branch diode circuits are connected together.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Mar 2, 2020
From: JPMORGAN CHASE BANK, N.A.
To: VERTIV CORPORATION (F/K/A ALBER CORP.); VERTIV IT SYSTEMS, INC. (F/K/A AVOCENT CORPORATION); VERTIV IT SYSTEMS, INC. (F/K/A AVOCENT FREMONT, LLC); VERTIV IT SYSTEMS, INC. (F/K/A AVOCENT HUNTSVILLE, LLC); VERTIV IT SYSTEMS, INC. (F/K/A AVOCENT REDMOND CORP.); ELECTRICAL RELIABILITY SERVICES, INC.; VERTIV CORPORATION (F/K/A EMERSON NETWORK POWER, ENERGY SYSTEMS, NORTH AMERICA, INC.); VERTIV CORPORATION (F/K/A LIEBERT CORPORATION)
Reel/Frame 052065/0666 →
SECURITY AGREEMENT Recorded Dec 2, 2016
From: ALBER CORP.; ASCO POWER TECHNOLOGIES, L.P.; AVOCENT CORPORATION; AVOCENT FREMONT, LLC; AVOCENT HUNTSVILLE, LLC; AVOCENT REDMOND CORP.; ELECTRICAL RELIABILITY SERVICES, INC.; EMERSON NETWORK POWER, ENERGY SYSTEMS, NORTH AMERICA, INC.; LIEBERT CORPORATION; LIEBERT NORTH AMERICA, INC.; NORTHERN TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 040797/0615 →
SECURITY AGREEMENT Recorded Dec 1, 2016
From: ALBER CORP.; ASCO POWER TECHNOLOGIES, L.P.; AVOCENT CORPORATION; AVOCENT FREMONT, LLC; AVOCENT HUNTSVILLE, LLC; AVOCENT REDMOND CORP.; ELECTRICAL RELIABILITY SERVICES, INC.; EMERSON NETWORK POWER, ENERGY SYSTEMS, NORTH AMERICA, INC.; LIEBERT CORPORATION; LIEBERT NORTH AMERICA, INC.; NORTHERN TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 040783/0148 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: BUSH, TERRY D.; DUNN, CHARLES; MILLER, JAMES; BLAIR, CHARLES F.
To: LIEBERT CORPORATION
Reel/Frame 036866/0436 →