Memory system including a battery powered buffer with a storage capacity of that buffer dependent on the voltage level of the battery

1. A memory system comprising:

a nonvolatile memory;

a buffer;

a battery configured to store energy supplied from an outside of the memory system; and

a processing circuit configured to,

after stop of the supply of energy from the outside, stop acceptance of a write request from the outside and save first data in the buffer into the nonvolatile memory using the energy stored in the battery,

after start of the supply of the energy from the outside and start of charging the energy to the battery, perform recovery of second data that correspond to first data saved in the nonvolatile memory,

after the recovery is completed and before a voltage of the battery reaches a set value, start the acceptance of a write request from the outside, start a write process in accordance with the accepted write request, the write process using the buffer, and restrict an amount of third data in the buffer referring to the voltage of the battery, the third data being dirty data stored in the buffer after the recovery is completed, wherein

the processing circuit computes a limit value based on the referred voltage and writes the third data in the buffer into the nonvolatile memory to prevent the amount of the third data in the buffer from exceeding the computed limit value, wherein

the nonvolatile memory includes a plurality of memory cells,

the processing circuit,

after the recovery is completed and before the voltage of the battery reaches the set value, writes, in first mode, the third data in the buffer into the nonvolatile memory,

after the recovery is completed and the voltage of the battery reaches the set value, writes, in second mode, the third data in the buffer into the nonvolatile memory, and

the second mode is a mode where a storage capacity of each of the plurality of memory cells is larger than that of the first mode.

2. The memory system according to claim 1 , wherein

the buffer includes a plurality of sub-buffers, and

the processing circuit shuts off the supply of energy to a sub-buffer in which no data are stored, among the plurality of sub-buffers.

3. The memory system according to claim 1 , wherein the processing circuit saves, in the first mode, the first data in the buffer into the nonvolatile memory.

4. The memory system according to claim 1 , wherein

the third data is data requested to write by the outside and not written to the nonvolatile memory yet, and

the processing circuit controls the acceptance of the third data to prevent the amount of the third data in the buffer from exceeding the computed limit value.

5. The memory system according to claim 1 , wherein

the processing circuit manages corresponding information between a logical address and a physical address, and generates changed information, the changed information being an updated part of the corresponding information or an added part of the corresponding information, and

the third data is the changed information.

6. The memory system according to claim 5 , wherein the processing circuit controls the updating of the corresponding information and prevents an amount of the changed information in the buffer from exceeding the computed limit value.

7. A memory system comprising:

a nonvolatile memory which includes a plurality of memory cells;

a buffer;

a battery configured to store energy supplied from an outside of the memory system;

a processing circuit configured to, after start of the supply of energy from the outside:

in a case where the battery is in a first state, write data in the buffer into the nonvolatile memory in a first mode, the first state being a state where a voltage of the battery is smaller than a set value; and

in a case where the battery is in a second state, write data in the buffer into the nonvolatile memory in a second mode, the second state being a state where the voltage of the battery is larger than the set value,

the second mode being a mode where a storage capacity of each of the plurality of memory cells is larger than that of the first mode.

8. The memory system according to claim 7 , wherein after the start of the supply of energy from the outside, the processing circuit

starts acceptance of a request from the outside,

starts a process in accordance with the accepted request, the process using the buffer, and

writes the data in the buffer into the nonvolatile memory using the energy stored in the battery after stop of the supply of energy from the outside.

9. The memory system according to claim 8 , wherein the processing circuit writes the data in the buffer in the first mode into the nonvolatile memory after the stop of the supply of energy from the outside.

10. The memory system according to claim 8 , wherein the processing circuit refers to the voltage of the battery and restricts an amount of the data in the buffer.

11. The memory system according to claim 10 , wherein the processing circuit

computes a limit value based on the referred voltage and

writes the data in the buffer into the nonvolatile memory to prevent the amount of the data in the buffer from exceeding the computed limit value.

12. The memory system according to claim 7 , wherein

the buffer includes a plurality of sub-buffers, and

the processing circuit shuts off the supply of energy to a sub-buffer in which no data are stored, among the plurality of sub-buffers.

13. The memory system according to claim 11 , wherein

the nonvolatile memory includes a first memory chip and a second memory chip, and wherein

after the start of the supply of energy from the outside, the processing circuit:

in a case where the battery is in the first state, writes the data in the buffer into the nonvolatile memory in a third mode; and

in a case where the battery is in the second state, writes the data in the buffer into the nonvolatile memory in a fourth mode,

the third mode being a mode where one of the first memory chip and the second memory chip is operated and the other is not operated at a time,

the fourth mode being a mode where both of the first memory chip and the second memory chip are operated at a time.

14. The memory system according to claim 11 , wherein

the data is data requested to write by the outside and not written to the nonvolatile memory yet, and

the processing circuit controls the acceptance of data requested to write by the outside, to prevent the amount of the data in the buffer from exceeding the computed limit value.

15. The memory system according to claim 11 , wherein

the processing circuit manages corresponding information between a logical address and a physical address, and generates changed information, the changed information being an updated part of the corresponding information or an added part of the corresponding information, and

the data is the changed information.

16. The memory system according to claim 15 , wherein the processing circuit controls the updating of the corresponding information and prevents an amount of the changed information in the buffer from exceeding the computed limit value.

17. A memory system comprising:

a nonvolatile memory;

a buffer;

a battery configured to store energy supplied from an outside of the memory system; and

a processing circuit configured to,

after stop of the supply of energy from the outside, stop acceptance of a write request from the outside and save first data in the buffer into the nonvolatile memory using the energy stored in the battery,

after start of the supply of the energy from the outside and start of charging the energy to the battery, perform recovery of second data that correspond to first data saved in the nonvolatile memory,

after the recovery is completed and before a voltage of the battery reaches a set value, start the acceptance of a write request from the outside, start a write process in accordance with the accepted write request, the write process using the buffer, and restrict an amount of third data in the buffer referring to the voltage of the battery, the third data being dirty data stored in the buffer after the recovery is completed, wherein

the processing circuit computes a limit value based on the referred voltage and writes the third data in the buffer into the nonvolatile memory to prevent the amount of the third data in the buffer from exceeding the computed limit value, wherein

the nonvolatile memory includes a first memory chip and a second memory chip, and

the processing circuit,

after the recovery is completed and before the voltage of the battery reaches the set value, writes, in a first mode, the third data in the buffer into the nonvolatile memory,

after the recovery is completed and the voltage of the battery reaches the set value, writes, in a second mode, the third data in the buffer into the nonvolatile memory,

the first mode is a mode where one of the first memory chip and the second memory chip is operated and the other is not operated at a time, and

the second mode is a mode where both of the first memory chip and the second memory chip are operated at a time.

18. The memory system according to claim 17 , wherein

the buffer includes a plurality of sub-buffers, and

the processing circuit shuts off the supply of energy to a sub-buffer in which no data are stored, among the plurality of sub-buffers.

19. The memory system according to claim 17 , wherein

the third data is data requested to write by the outside and not written to the nonvolatile memory yet, and

the processing circuit controls the acceptance of the third data to prevent the amount of the third data in the buffer from exceeding the computed limit value.

20. The memory system according to claim 17 , wherein

the processing circuit manages corresponding information between a logical address and a physical address, and generates changed information, the changed information being an updated part of the corresponding information or an added part of the corresponding information, and

the third data is the changed information.