Semiconductor memory device and method of operating the same
View Patent ↗A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional U-shaped structure. The peripheral circuit is configured to perform an erase operation on the pipe cell. A method of operating the semiconductor memory device includes selecting the memory string and performing the erase operation on the pipe cell.
1. A semiconductor memory device, comprising:
a memory string including a pipe cell, a plurality of memory cells configured to be arranged in series between a bit line and the pipe cell and between a source line and the pipe cell in a vertical direction to the pipe cell, and a channel layer having a three-dimensional U-shaped structure; and
a peripheral circuit configured to perform an erase operation on the pipe cell by applying a ground level voltage to the pipe cell when an erase voltage is applied to the plurality of the memory cells.
2. The semiconductor memory device of claim 1 ,
wherein the peripheral circuit performs the erase operation on the pipe cell when the erase operation is performed on the plurality of memory cells.
3. The semiconductor memory device of claim 1 ,
wherein the peripheral circuit is further configured to count an erase operation number of the plurality of memory cells and to perform the erase operation on the pipe cell if the erase operation number exceeds a reference value.
4. The semiconductor memory device of claim 1 , wherein the peripheral circuit is configured to include a counter for counting the number of times the erase operation performed on the plurality of memory cells.
5. The semiconductor memory device of claim 2 , wherein the the ground level voltage is applied to the pipe cell during the erase operation on the plurality of memory cells is performed.
6. A method of operating a semiconductor memory device including a pipe cell, a plurality of memory cells arranged in series between a bit line and the pipe cell and between a source line and the pipe cell in a vertical direction to the pipe cell respectively, and a channel layer with a three-dimensional U-shaped structure connecting the plurality of memory cells and the pipe cell, the method comprising:
applying a pre-charge voltage to the source line to supply hot holes to the channel layer;
applying an erase voltage to the source line to increase voltages of floating word lines of the plurality of memory cells; and
applying a ground level voltage to the pipe cell when the erase voltage is applied to the source line.
7. The method of claim 6 , further comprising:
applying a ground level voltage to the floating word lines of the plurality of memory cells to discharge trapped electrons to the channel layer.
8. The method of claim 6 , wherein the applying the ground voltage to the pipe cell comprises,
counting the number of times of an erase operation performed on the plurality of memory cells; and
applying, if the number of the erase operation exceeds a reference value, the ground level voltage to the pipe cell.
9. The method of claim 6 , further comprising:
applying a ground voltage to the pipe cell when the pre-charge voltage to the source line to supply hot holes to the channel layer.
10. A semiconductor memory device, comprising:
a memory string including a pipe cell, a plurality of memory cells configured to be arranged in series between a bit line and the pipe cell and between a source line and the pipe cell in a vertical direction to the pipe cell, and a channel layer having a three-dimensional U-shaped structure; and
a peripheral circuit configured to perform an erase operation on the pipe cell by applying a negative level voltage to the pipe cell.
11. The semiconductor memory device of claim 10 ,
the peripheral circuit performs the erase operation on the pipe cell when the erase operation is performed on the plurality of memory cells.
12. The semiconductor memory device of claim 10 ,
wherein the peripheral circuit is further configured to count an erase operation number of the plurality of memory cells and to perform the erase operation on the pipe cell if the erase operation number exceeds a reference value.
13. The semiconductor memory device of claim 10 ,
wherein the peripheral circuit is configured to include a counter for counting the number of times the erase operation performed on the plurality of memory cells.
14. The semiconductor memory device of claim 11 ,
wherein the negative level voltage is applied to the pipe cell during the erase operation on the plurality of memory cells is performed.
15. A method of operating a semiconductor memory device including a pipe cell, a plurality of memory cells arranged in series between a bit line and the pipe cell and between a source line and the pipe cell in a vertical direction to the pipe cell respectively, and a channel layer with a three-dimensional U-shaped structure connecting the plurality of memory cells and the pipe cell, the method comprising:
applying a pre-charge voltage to the source line to supply hot holes to the channel layer;
applying an erase voltage to the source line to increase voltages of floating word lines of the plurality of memory cells; and
applying a negative level voltage to the pipe cell when the erase voltage is applied to the source line.
16. The method of claim 15 , further comprising:
applying a ground level voltage to the floating word lines of the plurality of memory cells to discharge trapped electrons to the channel layer.
17. The method of claim 15 , wherein the applying the ground voltage to the pipe cell comprises,
counting the number of times of an erase operation performed on the plurality of memory cells; and
applying, if the number of the erase operation exceeds a reference value, the negative level voltage to the pipe cell.
18. The method of claim 15 , further comprising:
applying a negative voltage to the pipe cell when the pre-charge voltage to the source line to supply hot holes to the channel layer.