Method and apparatus for independent rise and fall waveform shaping
View Patent ↗Embodiments are directed to apparatuses and methods of waveform equalization. More specifically, various embodiments provide independent rise and fall waveform shaping equalization. There are other embodiments as well.
1. An apparatus comprising:
a main driver configured to generate a main driver current from an input signal;
a first adjustable delay block configured to generate a first delay signal from the input signal;
a rising-edge equalization driver configured to generate from the delay signal and the input signal, a first corresponding current pulse reflecting a rising edge transition in the input signal;
a second adjustable delay block configured to generate a second delay signal from the input signal;
a falling-edge equalization driver configured to generate from the delay signal and the input signal, a second corresponding current pulse reflecting a falling edge transition in the input signal; and
a final driver configured to combine the main driver current with the first corresponding current pulse and the second corresponding current pulse to generate an output having a waveform adjusted for the rising edge transition or the falling edge transition, wherein:
the rising-edge equalization driver is configured to generate a positive current pulse when there is a rising edge in the input signal;
the falling-edge equalization driver is configured to generate positive current pulse when there is a falling edge in the input signal; and the apparatus further comprises,
a second rising-edge equalization driver configured to generate a negative current pulse when there is a rising edge in the input signal;
a second falling-edge equalization driver configured to generate negative current pulse when there is a falling edge in the input signal.
2. An apparatus as in claim 1 wherein the first delay block comprises a chain of delay cells in communication with a multiple-phase mixer configured to produce the corresponding current pulse.
3. An apparatus as in claim 2 wherein a delay cell of the delay cell chain comprises a buffer.
4. An apparatus as in claim 3 wherein the buffer is in current mode logic (CML), CMOS, or emitter-couple logic (ECL).
5. An apparatus as in claim 2 wherein a delay cell of the delay cell chain is regulated in a loop.
6. An apparatus as in claim 5 wherein the loop is a delay-locked loop.
7. An apparatus as in claim 5 wherein the loop is a phase-locked loop.
8. An apparatus as in claim 1 wherein:
the first delay signal comprises a delay of the input signal; and
the second delay signal comprises a delay of an inverse of the input signal.
9. An apparatus as in claim 1 wherein the combiner comprises a transistor biased at a base of a DC voltage comprising a common mode voltage of the input signal.
10. An apparatus as in claim 1 wherein the input signal is received from a photo detector.
11. An apparatus as in claim 1 wherein the final driver comprises:
a first output transistor having a first node coupled to the rising-edge equalization driver and the falling edge equalization driver; and
a second output transistor having a second node coupled to the second rising-edge equalization driver and the second falling-edge equalization driver.
12. A method comprising:
generating, using a main driver, a main driver current from an input signal;
generating, using a first adjustable delay block, a first delay signal from a rising edge of the input signal;
generating, using a second adjustable delay block, a second delay signal from a falling edge of the input signal;
generating, using a first equalization driver, a first current pulse from the input signal and the first delay signal;
generating, using a second equalization driver, a second current pulse from the input signal the second delay signal;
combining, using a final driver, the main driver current, the first current pulse, and the second current pulse to produce an output having a waveform adjusted for the rising edge transition or the falling edge transition, wherein:
the first current pulse is positive; and
the second current pulse is positive; and the method further comprises, generating a negative third current pulse from a rising edge of the input signal; and
generating a negative fourth current pulse from a falling edge of the input signal.
13. A method as in claim 12 wherein the first delay signal is generated from a multiple-phase mixer in communication with a delay cell chain.
14. A method as in claim 13 wherein a delay cell of the delay cell chain comprises a buffer.
15. A method as in claim 14 wherein the buffer is in current mode logic (CML), CMOS, or emitter-couple logic (ECL).
16. A method as in claim 13 comprising regulating a delay cell of the delay cell chain in a loop.
17. A method as in claim 16 wherein the loop is a delay-locked loop.
18. A method as in claim 16 wherein the loop is a phase-locked loop.
19. A method as in claim 12 wherein:
the first delay signal comprises a delay of the input signal; and
the second delay signal comprises a delay of an inverse of the input signal.
20. A method as in claim 12 wherein the combining comprises biasing a transistor at a base of a DC voltage comprising a common mode voltage of the input signal.
21. A method as in claim 12 wherein the input signal is received from a photo detector.
22. A method as in claim 12 wherein the first and second current pulse are communicated to a first node of a first output transistor, and the third and fourth current pulse are communicated to a second node of a second output transistor.