Memory device including memory blocks and decoders to output memory block selection signals
View Patent ↗A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.
1. A memory device comprising:
a plurality of memory blocks; and
a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting at least one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting at least another one of the memory blocks.
2. The device according to claim 1 , wherein the memory blocks selected by the first and second block selection signals are adjacent memory blocks.
3. The device according to claim 1 , wherein the second decoder includes a first switch, a gate of the first switch being configured to receive a control signal from the first decoder.
4. The device according to claim 3 , wherein
the second decoder further includes a second switch connected in series with the first switch between an internal node and a ground node, the second block selection signal being generated by inverting a signal at the internal node.
5. The device according to claim 4 , further comprising additional decoders, wherein the decoders, including the first and second decoders and the additional decoders, are divided into an odd group and an even group, and the second switch is turned on when the first decoder that is outputting the first block selection signal belongs to the odd group and the second decoder belongs to the even group or when the first decoder that is outputting the first block selection signal belongs to the even group and the second decoder belongs to the odd group.
6. The device according to claim 5 , wherein the second decoder further includes third and fourth switches connected in series and in parallel with the first and second switches, between the internal node and the ground node, a gate of the third switch being configured to receive a control signal from a third decoder, which is another one of the decoders, and the fourth switch being turned on when the third decoder that is outputting a third block selection signal belongs to the odd group and the second decoder belongs to the even group or when the third decoder that is outputting the third block selection signal belongs to the even group and the second decoder belongs to the odd group.
7. The device according to claim 1 , wherein a decoder is provided for each of the memory blocks.
8. The device according to claim 1 , wherein a decoder is provided for at least two of the memory blocks, and the first decoder is configured to output additional block selection signals for selecting additional memory blocks.
9. A memory device operable in a first mode and a second mode comprising:
a plurality of memory blocks; and
a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting at least one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting at least another one of the memory blocks during the second mode but not during the first mode.
10. The device according to claim 9 , wherein the memory blocks selected by the first and second block selection signals are adjacent memory blocks.
11. The device according to claim 9 , wherein the second decoder includes a first switch, a gate of the first switch being configured to receive the first block selection signal, and a second switch connected in series with the first switch between an internal node and a ground node, the second block selection signal being generated by inverting a signal at the internal node.
12. The device according to claim 11 , further comprising additional decoders, wherein the decoders, including the first and second decoders and the additional decoders, are divided into an odd group and an even group, and the second switch is turned on during the second mode when the first decoder that is outputting the first block selection signal belongs to the odd group and the second decoder belongs to the even group or when the first decoder that is outputting the first block selection signal belongs to the even group and the second decoder belongs to the odd group.
13. The device according to claim 12 , wherein the second switch is not turned on during the first mode even when the first decoder that is outputting the first block selection signal belongs to the odd group and the second decoder belongs to the even group or when the first decoder that is outputting the first block selection signal belongs to the even group and the second decoder belongs to the odd group.
14. The device according to claim 13 , wherein the second decoder further includes third and fourth switches connected in series and in parallel with the first and second switches, between the internal node and the ground node, the third switch being turned on during the second mode, but not during the normal mode.
15. The device according to claim 9 , wherein a decoder is provided for each of the memory blocks.
16. The device according to claim 9 , wherein a decoder is provided for at least two of the memory blocks, and the first decoder is configured to output additional block selection signals for selecting additional memory blocks.