GaN structures
A semiconductor device is disclosed. The device includes a substrate including GaN, a two dimensional electron gas (2DEG) inducing layer on the substrate, and a lateral transistor on the 2DEG inducing layer. The lateral transistor includes source and drain contacts to the 2DEG inducing layer, a gate stack between the source and drain contacts, and a field plate between the gate and the drain contact. The device also includes one or more insulation layers on the 2DEG inducing layer, where the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, and a conductor on the insulation layers, where a first portion of the conductor is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than 200 nm.
1. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and
a capacitor, wherein at least a portion of a plate of the capacitor is formed at the same time and from the same material as the field plate,
wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
2. The device of claim 1 , wherein the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
3. The device of claim 1 , further comprising a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor.
4. The device of claim 1 , further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer on the 2DEG inducing layer is the second insulation layer.
5. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact; and
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, wherein at least one of the one or more insulation layers contacts the 2DEG inducing layer, and wherein at least one of the one or more insulation layers comprises an opening,
wherein the field plate comprises:
a first portion in the opening, and wherein the first portion of the field plate contacts the at least one insulation layer which contacts the 2DEG inducing layer, and
a second portion contacting the one or more insulation layers outside the opening,
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
6. The device of claim 5 , wherein the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
7. The device of claim 6 , wherein the second portion of the field plate and is spaced apart from the 2DEG inducing layer by the insulation layers by a distance greater than 200 nm.
8. The device of claim 5 , further comprising a capacitor, wherein at least a portion of the plate of the capacitor is formed at the same time and from the same material as the field plate of the lateral transistor.
9. The device of claim 5 , further comprising a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor.
10. The device of claim 5 , wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the at least one insulation layer which contacts the 2DEG inducing layer by a distance less than or equal to 200 nm.
11. The device of claim 5 , further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
12. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first portion of the field plate is spaced apart from the 2DEG inducing layer; and
a capacitor, wherein a plate of the capacitor is spaced apart from the 2DEG per QS inducing layer by the insulation layer,
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
13. The device of claim 12 , further comprising a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
14. The device of claim 12 , wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than or equal to 200 nm.
15. The device of claim 14 , wherein the second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm.
16. The device of claim 12 , further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the second insulation layer.
17. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers,
wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate; and
a capacitor, wherein at least a portion of a plate of the capacitor is formed at the same time and from the same material as the field plate of the lateral transistor.
18. The component of claim 17 , wherein the electronic circuit further comprises a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor.
19. The component of claim 17 , wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer on the 2DEG inducing layer is the second insulation layer.
20. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact; and
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, wherein at least one of the one or more insulation layers contacts the 2DEG inducing layer, and wherein at least one of the one or more insulation layers comprises an opening,
wherein the field plate comprises:
a first portion in the opening, and wherein the first portion of the field plate contacts the at least one insulation layer which contacts the 2DEG inducing layer, and
a second portion contacting the one or more insulation layers outside the opening,
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
21. The component of claim 20 , wherein the electronic circuit further comprises a capacitor, wherein at least a portion of a plate of the capacitor is formed at the same time and from the same material as the field plate of the lateral transistor.
22. The component of claim 20 , wherein the electronic circuit further comprises a diode having a field plate, wherein at least a portion of the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor.
23. The component of claim 20 , wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
24. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first portion of the field plate is spaced apart from the 2DEG inducing layer,
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate; and
a capacitor, wherein a plate of the capacitor is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
25. The component of claim 24 , further comprising a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
26. The component of claim 24 , wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than or equal to 200 nm.
27. The component of claim 24 , wherein the second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm.
28. The component of claim 24 , wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
29. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers; and
a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor,
wherein a first portion of the field plate of the lateral transistor is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
wherein a second portion of the field plate of the lateral transistor is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
wherein at least one of the one or more insulation layers contacts the first portion of the field plate of the lateral transistor and does not contact the second portion of the field plate of the lateral transistor.
30. The device of claim 29 , wherein the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
31. The device of claim 29 , further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer on the 2DEG inducing layer is the second insulation layer.
32. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first portion of the field plate is spaced apart from the 2DEG inducing layer,
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate; and
a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
33. The device of claim 32 , wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than or equal to 200 nm.
34. The device of claim 33 , wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm.
35. The device of claim 32 , further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the second insulation layer.
36. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers,
wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate; and
a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor.
37. The component of claim 36 , wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer on the 2DEG inducing layer is the second insulation layer.
38. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first n of the field plate is spaced apart from the 2DEG inducing layer,
wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate; and
a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
39. The component of claim 38 , wherein the first portion of the field plate of the lateral transistor is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than or equal to 200 nm.
40. The component of claim 38 , wherein a second portion of the field plate of the lateral transistor is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm.
41. The component of claim 38 , wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.