Dual sample-and-hold circuit with resistive gain
An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.
1. An image processing circuit, comprising:
a first sample-and-hold circuit configured to sample a first data from a pixel;
a second sample-and-hold circuit configured to sample a second data from the pixel;
a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a difference data; and
a current-mode analog-to-digital converter configured to convert the difference data from an analog form to a digital form.
2. The image processing circuit according to claim 1 , wherein:
the first and second sample-and-hold circuits respectively include a differential amplifier, a plurality of switches, and a sampling capacitor.
3. The image processing circuit according to claim 2 , wherein the respective plurality of switches includes:
a first feedback switch connected between an output of the differential amplifier and a first electrode of the sampling capacitor; and
a second feedback switch connected between the output of the differential amplifier and a second electrode of the sampling capacitor.
4. The image processing circuit according to claim 2 , wherein the plurality of switches includes a plurality of transistors.
5. The image processing circuit according to claim 1 , wherein:
the analog-to-digital converter is a current-mode sigma-delta analog-to-digital converter.
6. An image processing circuit, comprising:
a first dual sample-and-hold circuit configured to sample a first data and a second data from a first pixel;
a second dual sample-and-hold circuit configured to sample a third data and a fourth data from a second pixel;
a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a first difference data, and to receive the third data and the fourth data and output a second difference data; and
an analog-to-digital converter configured to convert the first and second difference data from an analog form to a digital form.
7. The image processing circuit according to claim 6 , wherein:
the first dual sample-and-hold circuit includes a first sample-and-hold circuit configured to sample the first data, a second sample-and-hold circuit configured to sample the second data, and a first plurality of switches; and
the second dual sample-and-hold circuit includes a third sample-and-hold circuit configured to sample the third data, a fourth sample-and-hold circuit configured to sample the fourth data, and a second plurality of switches.
8. The image processing circuit according to claim 7 wherein:
the first, second, third, and fourth sample-and-hold circuits respectively include a differential amplifier, a plurality of switches, and a sampling capacitor.
9. The image processing circuit according to claim 8 , wherein the respective plurality of switches includes:
a first feedback switch connected between an output of the differential amplifier and a first electrode of the sampling capacitor; and
a second feedback switch connected between the output of the differential amplifier and a second electrode of the sampling capacitor.
10. The image processing circuit according to claim 8 , wherein the plurality of switches includes a plurality of transistors.
11. The image processing circuit according to claim 6 , wherein:
the first pixel is in a first row of a pixel array; and
the second pixel is in a second row of the pixel array.
12. The image processing circuit according to claim 6 , wherein:
the analog-to-digital converter is a current-mode sigma-delta analog-to-digital converter.
13. An imaging device, comprising:
a pixel array including a first pixel and a second pixel; and
an image processing circuit, including:
a first dual sample-and-hold circuit configured to sample a first data and a second data from the first pixel;
a second dual sample-and-hold circuit configured to sample a third data and a fourth data from the second pixel;
a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a first difference data, and to receive the third data and the fourth data and output a second difference data; and
an analog-to-digital converter configured to convert the first and second difference data from an analog form to a digital form.
14. The imaging device according to claim 13 , wherein:
the first dual sample-and-hold circuit includes a first sample-and-hold circuit configured to sample the first data, a second sample-and-hold circuit configured to sample the second data, and a first plurality of switches; and
the second dual sample-and-hold circuit includes a third sample-and-hold circuit configured to sample the third data, a fourth sample-and-hold circuit configured to sample the fourth data, and a second plurality of switches.
15. The imaging device according to claim 14 wherein:
the first, second, third, and fourth sample-and-hold circuits respectively include a differential amplifier, a plurality of switches, and a sampling capacitor.
16. The image processing circuit according to claim 15 , wherein the respective plurality of switches includes:
a first feedback switch connected between an output of the differential amplifier and a first electrode of the sampling capacitor; and
a second feedback switch connected between the output of the differential amplifier and a second electrode of the sampling capacitor.
17. The image processing circuit according to claim 15 , wherein the plurality of switches includes a plurality of transistors.
18. The imaging device according to claim 13 , wherein:
the first pixel is in a first row of a pixel array; and
the second pixel is in a second row of the pixel array.
19. The imaging device according to claim 13 , wherein:
the analog-to-digital converter is a current-mode sigma-delta analog-to-digital converter.