Amplifier circuit, radio frequency receiver and mobile telecommunications device
View Patent ↗An amplifier circuit, comprises a first amplifier stage contributing to a power of an amplified signal and a second amplifier stage contributing to the power of the amplified signal. The first amplifier stage and the second amplifier stage share a transistor.
1. An amplifier circuit, comprising:
a first amplifier stage contributing to a power of an amplified signal;
a second amplifier stage contributing to the power of the amplified signal;
wherein the first amplifier stage and the second amplifier stage share a transistor,
a first transistor coupled to an input terminal of the amplifier circuit, the first transistor being part of the first amplifier stage;
a second transistor coupled to a supply voltage, the second transistor being part of the second amplifier stage;
wherein the transistor is coupled between the first transistor and the second transistor, and
wherein a drain of the transistor that is shared is coupled to an output terminal of the amplifier stage and to a drain of the second transistor.
2. The amplifier circuit of claim 1 , wherein the amplifier circuit is configured to tap a driving signal from the first amplifier stage to drive the second amplifier stage.
3. The amplifier circuit of claim 1 , wherein the transistor is used in a common gate mode within the first amplifier stage and in a common source mode within the second amplifier stage.
4. The amplifier circuit of claim 1 , wherein the first amplifier stage comprises an input amplifier having an output coupled to a source of the shared transistor.
5. The amplifier circuit of claim 4 , wherein the input amplifier is an inverting amplifier or a non inverting amplifier.
6. The amplifier circuit of claim 4 , wherein a signal tapped from the first amplifier stage to drive the second amplifier stage comprises a driving signal and is inverted with respect to a signal output by the input amplifier.
7. The amplifier circuit of claim 1 , wherein
the first amplifier stage corresponds to a cascode stage; and
the second amplifier stage corresponds to a transconductance stage.
8. The amplifier circuit of claim 1 , wherein a gate of the first transistor is coupled to the input terminal and wherein a drain of the first transistor is coupled to a source of the transistor that is shared.
9. The amplifier circuit of claim 8 , wherein the amplifier circuit is configured to tap a driving signal from the drain of the first transistor to drive the second amplifier stage.
10. The amplifier circuit of claim 1 , wherein the transistor that is shared and the second transistor are self biased.
11. An amplifier circuit, comprising:
a first amplifier stage contributing to a power of an amplified signal;
a second amplifier stage contributing to the power of the amplified signal; wherein the first amplifier stage and the second amplifier stage share a transistor
a first transistor coupled to an input terminal of the amplifier circuit, the first transistor being part of the first amplifier stage;
a second transistor coupled to a supply voltage, the second transistor being part of the second amplifier stage;
wherein the transistor is coupled between the first transistor and the second transistor,
wherein a gate of the first transistor is coupled to the input terminal and wherein a drain of the first transistor is coupled to a source of the transistor that is shared, and wherein
a gate of the second transistor is coupled to a first node;
a gate of the transistor that is shared is coupled to the first node; and
the first node is coupled to the output terminal via a first resistor.
12. The amplifier circuit of claim 1 , wherein the first transistor and the that is shared transistor are N-MOS Field effect transistors and wherein the second transistor is a P-MOS Field effect transistor.
13. A differential amplifier circuit, comprising:
a first amplifier circuit, comprising:
a first amplifier stage contributing to a power of a first amplified signal;
a second amplifier stage contributing to the power of the first amplified signal;
wherein the first amplifier stage and the second amplifier stage share a first transistor;
a second amplifier circuit, comprising:
a third amplifier stage contributing to a power of a second amplified signal;
a fourth amplifier stage contributing to the power of the second amplified signal;
wherein the third amplifier stage and the fourth amplifier stage share a second transistor,
wherein the first amplifier circuit and the second amplifier circuit are cross coupled,
wherein the first amplifier circuit is configured to tap a first driving signal from the third amplifier stage to drive the second amplifier stage, and
wherein the second amplifier circuit is configured to tap a second driving signal from the first amplifier stage to drive the fourth amplifier stage.
14. A differential amplifier circuit, comprising:
a first amplifier circuit, comprising:
a first amplifier stage contributing to a power of a first amplified signal;
a second amplifier stage contributing to the power of the first amplified signal;
wherein the first amplifier stage and the second amplifier stage share a first amplifier circuit transistor;
a second amplifier circuit, comprising:
a third amplifier stage contributing to a power of a second amplified signal;
a fourth amplifier stage contributing to the power of the second amplified signal;
wherein the third amplifier stage and the fourth amplifier stage share a second amplifier circuit transistor,
wherein the first amplifier circuit further comprises:
a first transistor coupled to an input terminal of the differential amplifier circuit, the first transistor being part of the first amplifier stage;
a second transistor coupled to a supply voltage, the second transistor being part of the second amplifier stage;
wherein the first amplifier circuit transistor is coupled between the first amplifier stage and the second amplifier stage; and
wherein the second amplifier circuit further comprises:
a third transistor coupled to an input terminal of the differential amplifier circuit, the third transistor being part of the third amplifier stage;
a fourth transistor coupled to the supply voltage, the fourth transistor being part of the fourth amplifier stage;
wherein the second amplifier circuit transistor is coupled between the third transistor and the fourth transistor,
wherein the first amplifier circuit transistor comprises a first shared transistor and the second amplifier circuit transistor comprises a second shared transistor.
15. The differential amplifier circuit of claim 14 , wherein
a drain of the first transistor is coupled to a source of the first shared transistor;
a drain of the first shared transistor is coupled to an output terminal and to a drain of the second transistor;
a drain of the third transistor is coupled to a source of the second shared transistor; and
a drain of the second shared transistor is coupled to a further output terminal and to a drain of the fourth transistor.
16. The differential amplifier circuit of claim 15 ,
wherein the first driving signal used to drive the second amplifier stage is tapped from the drain of the third transistor; and
wherein the second further driving signal used to drive the fourth amplifier stage is tapped from the drain of the first transistor.