Dual mode latch circuit
View Patent ↗A latch circuit that has a dynamic mode and a static mode is provided. Clock signals are generated specifically for a feedback path of a storage circuit in the latch circuit. The generated clock signals include transitions that cause clocked NMOS and PMOS devices in the feedback path to function, and for other input clock frequencies, the generated clock signals do not include transitions that cause the clocked PMOS and NMOS devices to be active, and have states that cause clocked PMOS and NMOS devices to be inactive.
1. A latch circuit having a first mode of operation in which the latch circuit functions as a static latch circuit, and having a second mode of operation in which the latch circuit functions as a dynamic latch circuit;
the latch circuit having inputs for receiving a latch circuit clock input and a data input and having an output for producing a latch circuit output, the latch circuit comprising:
a forward data path transmission circuit connected to receive the latch circuit clock input and the data input, the forward data path transmission circuit producing a data output, the forward data path transmission circuit having a transparent state activated by the clock input during which the data input is produced as the data output;
a storage circuit connected to receive the data output, the storage circuit having a forward path and a feedback path, the storage circuit having a clock input and producing the latch circuit output;
wherein during the first mode of operation the feedback path is active, and based on the clock input of the storage circuit, the storage circuit maintains a value output by the forward data path transmission circuit as part of the data output, such that the latch circuit functions as a static latch circuit; and
during the second mode of operation, the feedback path is inactive, and the latch circuit output is the data output after passing through the forward path of the storage circuit, such that the latch circuit functions as a dynamic latch circuit.
2. The latch circuit of claim 1 configured to adjust being in the first mode of operation or the second mode of operation based on a frequency of an input clock.
3. The latch circuit of claim 1 further comprising a circuit that controls whether the storage circuit is in the first mode of operation or the second mode of operation.
4. The latch circuit of claim 3 wherein the circuit that controls whether the storage circuit is in the first mode of operation or the second mode of operation comprises:
a frequency detector that determines a frequency of the clock input, and causes the storage circuit to be in the first mode of operation or the second mode of operation based on the determined frequency.
5. The latch circuit of claim 4 wherein the frequency detector causes the storage circuit to be in the first mode of operation when the frequency is below a threshold frequency and causes the storage circuit to be in the second mode of operation when the frequency is above a threshold frequency.
6. The latch circuit of claim 3 wherein the circuit that controls whether the storage circuit is in the first mode of operation or the second mode of operation comprises:
a clock producer circuit that receives the clock input of the latch circuit and produces the clock input to the storage circuit such that during the first mode of operation, the clock input to the storage circuit includes transitions that cause the feedback path to be active, and during the second mode of operation, the clock input to the storage circuit does not include transitions that cause the feedback path to be active, and the clock input to the storage circuit has a state that causes the feedback path to be inactive.
7. The latch circuit of claim 6 wherein the clock producer circuit comprises:
an inverter with a weak P transistor and a strong N transistor for processing the clock input; and
an inverter with a weak N transistor and a strong P transistor for processing an inverted version of the clock input.
8. A flip-flop comprising first and second latch circuits according to claim 7 with roles of the clock input and the inverted clock input reversed for the second latch circuit.
9. The latch circuit of claim 6 wherein the clock producer circuit comprises:
a first inverter with a weak P transistor and a strong N transistor for processing the clock input, and a second inverter that inverts the output of the first inverter; or
a first inverter with a weak N transistor and a strong P transistor for processing an inverted version of the clock input and a second inverter that inverts the output of the first inverter.
10. The latch circuit of claim 1 wherein the forward data path transmission circuit comprises a clocked inverter.
11. The latch circuit of claim 1 wherein the forward data path transmission circuit comprises an inverter and a transmission gate.
12. The latch circuit of claim 1 wherein:
the feedforward path comprises a first inverter;
the feedback path connects an output of the first inverter to an input of the first inverter and comprises a clocked inverter.
13. The latch circuit of claim 1 wherein:
the feedforward path comprises a first inverter;
the feedback path connects an output of the first inverter to an input of the first inverter and comprises an inverter and a transmission gate.
14. A flip-flop comprising first and second latch circuits according to claim 1 .
15. An integrated circuit comprising the latch circuit of claim 1 .
16. A SerDes (serializer deserializer) comprising:
a serializer;
a deserializer comprising a demultiplexer comprising the latch circuit of claim 1 .
17. The SerDes of claim 16 comprising a DFE (decision feedback equalizer), the DFE comprising said latch circuit.
18. A circuit comprising:
at least one flip-flop, each flip flop comprising first and second latch circuits according to claim 1 ;
a clock producer circuit comprising:
an inverter with a weak P transistor and a strong N transistor that processes the input clock and outputs a third clock;
an inverter with a weak N transistor and a strong P transistor that processes an inverted version of the input clock and outputs a fourth clock;
an inverter with a weak P transistor and a strong N transistor that processes the inverted version of the input clock and outputs a fifth clock;
an inverter with a weak N transistor and a strong P transistor that processes the input clock and produces a sixth clock;
wherein the storage circuit of each first latch circuit operates based on the third clock and the fourth clock, and the storage circuit of each second latch circuit operates based on the fifth clock and the sixth clock.
19. A circuit comprising:
at least one flip-flop, each flip flop comprising first and second latch circuits according to claim 1 ;
a clock producer circuit comprising:
an inverter with a weak P transistor and a strong N transistor that processes the input clock and outputs a third clock;
an inverter that inverts the third clock to produce a fourth clock;
an inverter with a weak P transistor and a strong N transistor that processes the inverted version of the input clock and outputs a fifth clock;
an inverter that inverts the fifth clock to produce a sixth clock;
wherein the storage circuit of each first latch circuit operates based on the third clock and the fourth clock, and the storage circuit of each second latch circuit operates based on the fifth clock and the sixth clock.
20. The latch circuit of claim 3 wherein the circuit that controls whether the storage circuit is in the first mode of operation or the second mode of operation receives a control input, and controls whether the storage circuit is in the first mode of operation or the second mode of operation based on the control input.
21. A flip-flop comprising first and second latch circuits according to claim 1 , and further comprising a clock producer circuit that controls whether the storage circuit of the first latch circuit is in the first mode of operation or the second mode of operation, and controls whether the storage circuit of the second latch circuit is in the first mode of operation or the second mode of operation.
22. A method comprising:
providing a data input to a clocked inverter or an inverter in combination with a transmission gate, based on an input clock and an inverted input clock;
passing an output of the clocked inverter or an inverter in combination with a transmission gate to a storage circuit having an inverter in a forward path and a clocked inverter or an inverter in combination with a transmission gate in a feedback path, the feedback path having a clocked NMOS device and a clocked PMOS device
generating clock signals for the clocked NMOS device and the clocked PMOS device from the input clock and the inverted input clock such that for some input clock frequencies, the generated clock signals include transitions that cause the clocked NMOS and PMOS devices in the feedback path to be active, and for other input clock frequencies, the generated clock signals do not include transitions that cause the clocked PMOS and NMOS devices to be active, and have states that cause clocked PMOS and NMOS devices to be inactive.