Semiconductor devices having gate structures and methods of manufacturing the same
Semiconductor devices are provided including an active layer, a gate structure, a spacer, and a source/drain layer. The active layer is on the substrate and includes germanium. The active layer includes a first region having a first germanium concentration, and a second region on both sides of the first region. The second region has a top surface getting higher from a first portion of the second region adjacent to the first region toward a second portion of the second region far from the first region, and has a second germanium concentration less than the first germanium concentration. The gate structure is formed on the first region of the active layer. The spacer is formed on the second region of the active layer, and contacts a sidewall of the gate structure. The source/drain layer is adjacent to the second region of the active layer.
1. A semiconductor device, comprising:
an active layer including germanium on a substrate, the active layer including:
a first region having a first germanium concentration; and
a second region on both sides of the first region, the second region having a top surface that is higher than a top surface of the first region, the second region having a first portion adjacent the first region and a second portion higher than the top surface of the first region, and the second region having a second germanium concentration less than the first germanium concentration;
a gate structure on the first region of the active layer;
a spacer on the second region of the active layer, the spacer contacting a sidewall of the gate structure; and
a source/drain layer adjacent to the second region of the active layer,
wherein a bottom surface of the spacer gets higher from a first portion of the spacer adjacent to the first region toward a second portion of the spacer far from the first region.
2. The semiconductor device of claim 1 , wherein the first germanium concentration is substantially constant in the first region, and the second germanium concentration decreases from the first portion toward the second portion of the second region.
3. The semiconductor device of claim 1 , wherein the source/drain layer has a third germanium concentration, and a maximum value of the third germanium concentration is more than that of the first germanium concentration.
4. The semiconductor device of Claim 1 , wherein the spacer has a recess in a horizontal direction at an inner sidewall thereof contacting the sidewall of the gate structure.
5. The semiconductor device of Claim 1 , wherein the spacer has a vertical inner sidewall contacting the sidewall of the gate structure.
6. The semiconductor device of claim 1 , wherein the gate structure has a gate electrode including a metal, and a high-k dielectric layer pattern surrounding a bottom and a sidewall of the gate electrode.
7. The semiconductor device of claim 6 , wherein the gate structure further includes a silicon oxide layer pattern between the active layer and the high-k dielectric layer pattern.
8. The semiconductor device of claim 7 , wherein the silicon oxide layer pattern is formed only on the first region of the active layer.
9. The semiconductor device of claim 7 , wherein the silicon oxide layer pattern is formed not only on the first region of the active layer but also on at least a portion of the second region of the active layer.
10. The semiconductor device of claim 6 , wherein the sidewall of the gate structure has a protrusion in a horizontal direction.
11. The semiconductor device of claim 6 , wherein the sidewall of the gate structure has a vertical sidewall.
12. The semiconductor device of claim 1 , wherein each of the active layer and the source/drain layer includes silicon-germanium.
13. The semiconductor device of claim 1 , wherein the source/drain layer is highly doped with p-type impurities, and the second region of the active layer is lightly doped with p-type impurities.
14. The semiconductor device of claim 1 , wherein a top surface of the first region of the active layer is flat and is not higher than a top surface of the second region of the active layer.
15. The semiconductor device of claim 1 , further comprising an isolation layer pattern on the substrate, the isolation layer pattern surrounding a sidewall of the active layer.
16. The semiconductor device of claim 15 , wherein a top surface of the isolation layer pattern is lower than that of the active layer.
17. A semiconductor device, comprising:
an active layer including germanium on a substrate, the active layer including:
a first region having a first germanium concentration; and
a second region on both sides of the first region, the second region having a second germanium concentration decreasing from the first germanium concentration from a first portion of the second region adjacent to the first region toward a second portion of the second region remote from the first region;
a gate structure on the first region of the active layer;
a spacer on the second region of the active layer, the spacer contacting a sidewall of the gate structure; and
a source/drain layer adjacent to the second region of the active layer,
wherein a bottom surface of the spacer gets higher from a first portion of the spacer adjacent to the first region toward a second portion of the spacer far from the first region.
18. The semiconductor device of claim 17 , wherein a top surface of the second region of the active layer is higher than a top surface of the first region.