IP Library Granted Patent US 9,692,370
Granted Patent B2
US 9,692,370 · App. 14/862,144 · Granted Jun 27, 2017

Biasing circuitry

Inventors: Jui-Chieh Chiu (Taoyuan, TW); Fan-Hsiu Huang (New Taipei, TW); Chih-Wen Huang (Taoyuan, TW)
Assignee: WIN Semiconductors Corp.
H03F3/21H03F1/303H03F3/19H03F2200/27H03F2200/294H03F2200/451
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Quick Facts
Patent No.
US 9,692,370
App. No.
14/862,144
Granted
Jun 27, 2017
Kind
B2
Abstract

A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier.

Claims (11)

1. A biasing circuitry, configured to provide a bias point for an amplifying circuit, the biasing circuitry comprising:

a biasing module, formed within a first die via a semiconductor process, the biasing module electrically connected to the amplifying circuit and configured to provide the bias point to the amplifying circuit; and

a control series, disposed outside the first die, having an end electrically connected to a positive voltage and another end electrically connected to the biasing module, the control series comprising:

a voltage-drop unit, configured to adjust the bias point of the amplifying circuit; and

a switch unit, connected to the voltage drop unit in series, controlled by a control voltage and configured to be conducted or cutoff, so as to control the amplifying circuit to be enabled or disabled.

2. The biasing circuitry of claim 1 , wherein the amplifying circuit is a power amplifier or a low noise amplifier.

3. The biasing circuitry of claim 1 , wherein the amplifying circuit comprises a heterojunction bipolar transistor (HBT) or a high electron mobility transistor (HEMT).

4. The biasing circuitry of claim 1 , wherein the semiconductor process is a Gallium Arsenide (GaAs) semiconductor process.

5. The biasing circuitry of claim 1 , wherein the switch unit is a field effect transistor (FET) or a high electron mobility transistor (HEMT).

6. The biasing circuitry of claim 5 , wherein a gate of the switch unit is configured to receive the control voltage.

7. The biasing circuitry of claim 1 , wherein the voltage-drop unit comprises at least a resistor, configured to adjust the bias point of the amplifying circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2015
From: CHIU, JUI-CHIEH; HUANG, FAN-HSIU; HUANG, CHIH-WEN
To: WIN SEMICONDUCTORS CORP.
Reel/Frame 036627/0585 →
Priority Claims (1)
TW 104119661 A · Jun 17, 2015 · national
Continuity (1)
Related Publication 20160373068A1 · Dec 22, 2016