Detection system and method for baseboard management controller
View Patent ↗A detection system for a baseboard management controller (BMC) provides a motherboard and a BMC. The motherboard sends a detection command to the BMC, the command requiring the BMC to send a response value to the motherboard. A determination unit determines whether the motherboard receives the response value within a preset time. When the motherboard does not receive the response value within the preset time, the determination unit determines that the BMC works abnormally and issues warnings. A detection method is also provided.
1. A detection system comprising:
a baseboard management controller (BMC) comprising a first sending unit and a first receiving unit; and
a motherboard comprising:
a second sending unit configured for sending a detection command to the first receiving unit of the BMC, the detection command configured for controlling the first sending unit of the BMC to send back a response value;
a second receiving unit configured for obtaining the response value from the BMC;
a determination unit configured to determine whether the second receiving unit receives the response value from the BMC within a preset time;
wherein when the second receiving unit receives the response value within the preset time, the determination unit determines that the BMC works normally;
wherein when the second receiving unit does not receive the response value within the preset time, the determination unit determines that the BMC works abnormally; and
wherein the motherboard further comprises a warning unit, and the warning unit displays the warning information when the determination unit determines that the BMC works abnormally.
2. The detection system of claim 1 , wherein when the second receiving unit does not receive the response value within the preset time, the second sending unit of the motherboard sends a system control interrupt (SCI) command to the BMC to reset the BMC.
3. The detection system of claim 2 , wherein the motherboard comprises a flash memory, when the second receiving unit does not receive the response value within the preset time, the motherboard stores a system event log (SEL) to the flash memory.
4. The detection system of claim 1 , wherein the motherboard communicates with the BMC through an intelligent platform management interface (IPMI).
5. The detection system of claim 1 , wherein the motherboard communicates with the BMC through an inter-integrated circuit (I2C) bus.
6. The detection system of claim 1 , wherein the second sending unit sends the detection command to the BMC per time interval.
7. The detection system of claim 6 , wherein the time interval is longer than the preset time.
8. A detection method comprising:
sending a detection command to a first receiving unit of a baseboard management controller (BMC) by a second sending unit of a motherboard, and controlling a first sending unit of the BMC to send back a response value to a second receiving unit of the motherboard by the detection command;
determining whether the second receiving unit of the motherboard receives the response value from the BMC within a preset time by a determination unit of the motherboard;
determining that the BMC works normally by the determination unit when the second receiving unit receives the response value within the preset time;
determining that the BMC works abnormally by the determination unit when the second receiving unit does not receive the response value within the preset time; and
displaying a warning information by a warning unit when the BMC is determined to work abnormally.
9. The detection method of claim 8 , wherein the detection method further comprises sending a system control interrupt (SCI) command to the BMC to reset the BMC by the second sending unit of the motherboard when the second receiving unit does not receive the response value within the preset time.
10. The detection method of claim 8 , wherein the detection method further comprises communicating with the BMC through an intelligent platform management interface (IPMI) by the motherboard.
11. The detection method of claim 8 , wherein the detection method further comprises storing a system event log (SEL) to a flash memory by the motherboard when the second receiving unit does not receive the response value within the preset time.
12. The detection method of claim 8 , wherein the detection method further comprises sending the detection command to the BMC per time interval by the second sending unit.
13. The detection method of claim 8 , wherein the detection method further comprises communicating with the BMC through an inter-integrated circuit (I2C) bus by the motherboard.