Systems and devices for quantum processor architectures
View Patent ↗Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Angular deviations between qubits in one set may allow qubits in the same set to cross one another. Each unit cell is positioned proximally adjacent at least one other unit cell. Communicatively coupling between qubits is realized through respective intra-cell and inter-cell coupling devices.
1. A quantum processor comprising:
a plurality of unit cells tiled over an area such that each unit cell is positioned adjacent to at least one other unit cell, each unit cell comprising:
a first set of qubits and a second set of qubits, each qubit in the first set and the second set of qubits comprising:
a respective loop of material that is superconductive at a critical temperature; and
at least one respective Josephson Junction that interrupts the loop of material, wherein a first portion of the loop of material of a first qubit in the first set of qubits is oriented at an angle greater than zero degrees and less than ninety degrees to at least a portion of the loop of material of at least one qubit in the second set of qubits, the first qubit in the first set of qubits crossing at least one qubit in the second set of qubits, and the first portion of the first qubit in the first set of qubits crossing at least one other qubit in the first set of qubits;
a first set of intra-cell coupling devices, wherein each coupling device in the first set of intra-cell coupling devices is positioned proximate a respective point where a respective one of qubits in the first set of qubits crosses one of the qubits in the second set of qubits and provides controllable communicative coupling between the qubit in the first set of qubits and the respective qubit in the second set of qubits; and
a second set of intra-cell coupling devices, wherein each coupling device in the second set of intra-cell coupling devices is positioned proximate a respective point at which each at least one qubit in the first set of qubits crosses the at least one other qubit in the first set of qubits and provides controllable communicative coupling between the at least one qubit in the first set of qubits and the at least one other qubit in the first set of qubits.
2. The quantum processor of claim 1 wherein each unit cell is positioned horizontally adjacent, vertically adjacent, and/or diagonally adjacent at least one other unit cell.
3. The quantum processor of claim 2 wherein each unit cell is positioned adjacent at least three other unit cells such that each unit cell is positioned horizontally adjacent at least one other unit cell, vertically adjacent at least one other cell, and diagonally adjacent at least one other cell.
4. The quantum processor of claim 1 wherein the qubits in the second set of qubits are parallel to one another, the first qubit in the first set of qubits comprising the first portion oriented at an angle greater than zero degrees and less than ninety degrees to the qubits in the second set of qubits, and at least one other portion oriented perpendicular to the qubits in the second set of qubits, the first portion crossing the at least one other qubit in the first set of qubits.
5. The quantum processor of claim 1 , further comprising an inter-cell coupling device positioned between a pair of qubits, a first member qubit of the pair of qubits in a first unit cell, and a second member qubit of the pair of qubits in a second unit cell, the inter-cell coupling device which provides controllable communicative coupling between the pair of qubits.
6. The quantum processor of claim 5 wherein the second unit cell is adjacent to the first unit cell.
7. The quantum processor of claim 6 wherein the second unit cell is horizontally or vertically adjacent to the first unit cell.
8. The quantum processor of claim 6 wherein the second unit cell is diagonally adjacent to the first unit cell.
9. The quantum processor of claim 1 wherein, in each unit cell, the first set of qubits includes at least four qubits and the second set of qubits includes at least four qubits, such that the unit cell includes at least eight qubits.
10. The quantum processor of claim 1 wherein each of the coupling devices of the first set of intra-cell coupling devices is positioned to selectively directly inductively couple a respective one of the qubits of the first set of qubits with a respective one of the qubits of the second set of qubits; and
each of the coupling devices of the second set of intra-cell coupling devices positioned to selectively directly inductively couple a respective one of the qubits of the first set of qubits with a respective another one of the qubits of the first set of qubits.
11. The quantum processor of claim 10 , further comprising:
a third set of intra-cell coupling devices, each of the couplers of the third set of intra-cell coupling devices positioned to selectively directly inductively couple a respective one of the qubits of the second set of qubits with a respective another one of the qubits of the second set of qubits.
12. The quantum processor of claim 1 wherein the quantum processor comprises a multi-layered integrated circuit.
13. The quantum processor of claim 12 wherein the quantum processor comprises a superconducting quantum processor and the multi-layered integrated circuit comprises a multi-layered superconducting integrated circuit.