IP Library Granted Patent US 9,774,349
Granted Patent B2
US 9,774,349 · App. 14/863,075 · Granted Sep 26, 2017

Optimized code table signaling for authentication to a network and information system

Inventor: Bruce Conway (Williston, ND)
Assignee: AgilePQ, Inc.
H03M7/3082H03M7/42H03M7/6052H03M13/00H03M13/11H03M13/25H03M13/251H03M13/353H03M13/611H04L1/006H04L1/0009H04L1/0041H04L1/0042H04L1/0043H04L1/0061H04L1/0075H04L9/00H04L25/4915H04L27/3416
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Quick Facts
Patent No.
US 9,774,349
App. No.
14/863,075
Granted
Sep 26, 2017
Kind
B2
Abstract

In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

Claims (53)

1. A system comprising:

a network interface;

a processor; and

a non-transient memory medium operatively coupled to the processor, wherein the non-transient memory medium is configured to store a plurality of instructions configured to program the processor to:

receive a digital bit stream;

generate an initial gateway portion and an initial composite portion;

generate a gateway mask based on the initial gateway portion;

apply the gateway mask to the initial gateway portion to generate a final gateway portion;

apply the gateway mask to the initial composite portion to generate a final composite portion;

interleave a data vector with the final gateway portion and the final composite portion to generate a header portion;

transform the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises the header portion and a data portion; and

provide the encoded digital bit stream to the network interface for transmission.

2. The system of claim 1 , wherein the processor is further configured to apply an m-element vector table to the digital bit stream.

3. The system of claim 2 , wherein the processor is further configured to apply the m-element vector table to manage at least one of realized data throughput, bit energy, or signal range.

4. The system of claim 1 , wherein the processor is further configured to perform a table lookup for the digital bit stream.

5. The system of claim 1 , wherein the processor is further configured to manage one or more tasks to modify data transfer performance in an existing information system.

6. The system of claim 1 , wherein the processor is further configured to:

generate a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and

add the plurality of additional bits to the encoded digital bit stream.

7. The system of claim 1 , wherein the network interface comprises an information system.

8. The system of claim 7 , wherein the information system is a bound information system.

9. The system of claim 7 , wherein the information system is an unbound information system.

10. A non-transitory computer-readable memory medium configured to store instructions thereon that when loaded by a processor, cause the processor to:

receive a digital bit stream;

generate an initial gateway portion and an initial composite portion;

generate a gateway mask based on the initial gateway portion;

apply the gateway mask to the initial gateway portion to generate a final gateway portion;

apply the gateway mask to the initial composite portion to generate a final composite portion;

interleave a data vector with the final gateway portion and the final composite portion to generate a header portion;

transform the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises the header portion and a data portion; and

provide the encoded digital bit stream to a network interface for transmission.

11. The non-transitory computer-readable memory medium of claim 10 , wherein the instructions stored thereon further cause the processor to apply an m-element vector table to the digital bit stream.

12. The non-transitory computer-readable memory medium of claim 11 , wherein the instructions stored thereon further cause the processor to apply the m-element vector table to manage at least one of realized data throughput, bit energy, or signal range.

13. The non-transitory computer-readable memory medium of claim 10 , wherein the instructions stored thereon further cause the processor to perform a table lookup for the digital bit stream.

14. A computer-implemented method executable in a network environment, the network environment comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor, wherein the non-transient memory medium is configured to store a plurality of instructions configured to program the processor, the method comprising:

receiving, by the processor, a digital bit stream;

generating, by the processor, an initial gateway portion and an initial composite portion;

generating, by the processor, a gateway mask based on the initial gateway portion;

applying, by the processor, the gateway mask to the initial gateway portion to generate a final gateway portion;

applying, by the processor, the gateway mask to the initial composite portion to generate a final composite portion;

interleaving, by the processor, a data vector with the final gateway portion and the final composite portion to generate a header portion;

transforming, by the processor, the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises the header portion and a data portion; and

providing, by the processor, the encoded digital bit stream to the network interface for transmission.

15. The method of claim 14 , further comprising applying, by the processor, an m-element vector table to the digital bit stream.

16. The method of claim 15 , further comprising applying, by the processor, the m-element vector table to manage at least one of realized data throughput, bit energy, or signal range.

17. The method of claim 14 , further comprising performing, by the processor, a table lookup for the digital bit stream.

18. The method of claim 14 , further comprising:

managing, by the processor, one or more tasks to modify data transfer performance; and

providing, by the processor, an industry-standards agnostic interface to an existing information system.

19. The method of claim 14 , further comprising:

generating, by the processor, a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and

adding, by the processor, the plurality of additional bits to the encoded digital bit stream.

20. The method of claim 14 , further comprising providing, by the processor, the encoded digital bit stream to an information system.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2022
From: AGILEPQ, INC.
To: TMT ADVISORS, LLC
Reel/Frame 058595/0304 →
CHANGE OF NAME Recorded Sep 20, 2016
From: OPTCTS, INC.
To: AGILEPQ, INC.
Reel/Frame 040091/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: CONWAY, BRUCE
To: OPTCTS, INC.
Reel/Frame 037595/0865 →
Continuity (3)
Continuation 14310652 · Jun 20, 2014
Provisional Application 61862745 · Aug 6, 2013
Related Publication 20160254877A1 · Sep 1, 2016