IP Library Granted Patent US 9,548,729
Granted Patent B2
US 9,548,729 · App. 14/866,193 · Granted Jan 17, 2017

Switching circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,548,729
App. No.
14/866,193
Granted
Jan 17, 2017
Kind
B2
Abstract

A switching circuit includes a driver circuit DRV 2 that outputs voltage for turning on and off a first transistor switch M 2 , positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV 2 to output a first voltage that turns the first transistor switch M 2 on upon an output voltage of the driver circuit DRV 2 rising while the first transistor switch M 2 is off and to cause the driver circuit DRV 2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV 2 dropping after the driver circuit DRV 2 outputs the first voltage.

Claims (36)

1. A switching circuit comprising:

a driver circuit configured to output voltage for turning on and off a first transistor switch, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground;

a control circuit configured to cause the driver circuit to output a first voltage that turns the first transistor switch on upon an output voltage of the driver circuit rising while the first transistor switch is off and to cause the driver circuit to suspend output of the first voltage upon the output voltage of the driver circuit dropping after the driver circuit outputs the first voltage; and

an up/down counter and a variable delay circuit, wherein an output of the up/down counter is coupled to an input of the variable delay circuit, and an output of the variable delay circuit is coupled to an input of the driver circuit.

2. The switching circuit of claim 1 , wherein the driver circuit includes a variable resistor, and resistance of the variable resistor changes in response to a signal from the control circuit.

3. The switching circuit of claim 2 , wherein when the first transistor switch is on, the driver circuit decreases the resistance of the variable resistor until the output voltage falls below the first voltage and increases the resistance of the variable resistor upon the output voltage becoming equal to or less than the first voltage.

4. The switching circuit of claim 1 , wherein the variable delay circuit is configured to delay output of the first voltage, from the driver circuit to the first transistor switch, based on the output voltage of the driver circuit.

5. The switching circuit of claim 1 , wherein the first transistor switch is a metal-oxide-semiconductor field-effect transistor (MOSFET) controlled by voltage supplied to a gate thereof.

6. The switching circuit of claim 1 , further comprising:

an auxiliary switch coupled in parallel with the first transistor switch at the low potential side with respect to the load; and

an auxiliary driver circuit configured to output voltage for turning on and off the auxiliary switch.

7. The switching circuit of claim 1 , further comprising:

a second transistor switch, positioned at a high potential side with respect to the load, among the plurality of transistor switches disposed in series between the input voltage and the ground; and

a high-side driver circuit configured to output voltage for turning on and off the second transistor switch.

8. The switching circuit of claim 7 , further comprising an output node between the second transistor switch and the first transistor switch, wherein an output load voltage at the output node is provided to the load.

9. The switching circuit of claim 1 , wherein an output load voltage of the switching circuit is coupled to the load in a switching regulator.

10. A method of attenuating ringing in a switching circuit, the method comprising:

causing a driver circuit, of the switching circuit, to output a first voltage that turns a first transistor switch on upon an output voltage of the driver circuit rising while the first transistor switch is off;

wherein the first transistor switch, among a plurality of transistor switches disposed in series between an input voltage and a ground, is positioned at a low potential side with respect to a load;

causing the driver circuit to suspend output of the first voltage upon the output voltage of the driver circuit dropping after the driver circuit outputs the first voltage; and

using an up/down counter coupled to a variable delay circuit to delay output of the first voltage.

11. The method of claim 10 , further comprising:

detecting a self turn-on state and a non-self turn-on state of the driver circuit; and

changing resistance of a variable resistor of the driver circuit in response to detecting the self turn-on state or the non-self turn state.

12. The method of claim 11 , further comprising increasing the resistance of the variable resistor in response to the driver circuit switching from the non-self turn-on state to the self turn-on state.

13. The method of claim 11 , further comprising decreasing the resistance of the variable resistor in response to the driver circuit switching from the self turn-on state to the non-self turn-on state.

14. The method of claim 10 , further comprising matching a timing at which ringing occurs in the switching circuit with a timing at which current flows to the ground.

15. The method of claim 10 , further comprising delaying output of the first voltage, from the driver circuit to the first transistor switch, based on the output voltage of the driver circuit.

16. An apparatus comprising:

a load; and

a switching regulator coupled to provide voltage to the load, the switching regulator comprising:

a driver circuit configured to output voltage for turning on and off a first transistor switch, positioned at a low potential side with respect to the load, among a plurality of transistor switches disposed in series between an input voltage and a ground;

a control circuit configured to cause the driver circuit to output a first voltage that turns the first transistor switch on upon an output voltage of the driver circuit rising while the first transistor switch is off and to cause the driver circuit to suspend output of the first voltage upon the output voltage of the driver circuit dropping after the driver circuit outputs the first voltage; and

an up/down counter and a variable delay circuit, wherein an output of the up/down counter is coupled to an input of the variable delay circuit, and an output of the variable delay circuit is coupled to an input of the driver circuit.

17. The apparatus of claim 16 , wherein the load is a control circuit.

18. The apparatus of claim 16 , wherein the switching regulator is configured as an on-board power supply.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 052487/0808 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST Recorded Dec 5, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 051209/0721 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 16, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING
Reel/Frame 047797/0854 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY EXECUTION DATE AND RECEIVING PARTY DATA PREVIOUSLY RECORDED ON REEL 040244 FRAME 0226. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 9, 2016
From: MIYAMAE, TORU
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 040874/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2016
From: MIYAMAE, TORU
To: SPANSION LLC
Reel/Frame 040244/0226 →
SECURITY INTEREST Recorded Aug 15, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039676/0237 →