IP Library Granted Patent US 10,803,165
Granted Patent B2
US 10,803,165 · App. 14/866,860 · Granted Oct 13, 2020

Detection of shellcode

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Quick Facts
Patent No.
US 10,803,165
App. No.
14/866,860
Granted
Oct 13, 2020
Kind
B2
Abstract

Particular embodiments described herein provide for an electronic device that can be configured to monitor code as it executes. The code can include self-modifying code. The system can log an event if the self-modifying code occurred in a GetPC address region.

Claims (57)

1. At least one non-transitory machine readable medium comprising one or more instructions that when executed by at least one processor, cause the at least one processor to:

detect execution of a GetPC instruction sequence;

in response to detecting the execution of the GetPC instruction sequence, return to the GetPC instruction sequence a poison GetPC address in a GetPC address region instead of a current PC address, wherein the poison GetPC address is an identifiable invalid address;

determine whether self-modifying code is detected;

monitor, based on a determination that self-modifying code is detected, code as it executes to detect whether execution of the self-modifying code occurred at the poison GetPC address in the GetPC address region; and

based on a determination that the execution of the self-modifying code occurred at the poison GetPC address in the GetPC address region:

log an event; and

analyze the code for malware.

2. The at least one machine readable medium of claim 1 , wherein the poison GetPC address causes a memory fault.

3. The at least one machine readable medium of claim 1 , further comprising one or more instructions that when executed by at least one processor, further cause the at least one processor to:

log the event based on a determination that a memory fault exception occurred during translation and the memory fault translation matches with the identifiable invalid address.

4. The at least one machine readable medium of claim 1 , further comprising one or more instructions that when executed by at least one processor, further cause the at least one processor to:

communicate the code to a security module based on a determination that the self-modifying code occurred at the poison GetPC address in the GetPC address region.

5. The at least one machine readable medium of claim 1 , further comprising one or more instructions that when executed by at least one processor, further cause the at least one processor to:

determine whether an exception occurred during a translation of the code; and

log the event based on a determination that the exception occurred at the identifiable invalid address.

6. The at least one machine readable medium of claim 1 , further comprising one or more instructions that when executed by at least one processor, further cause the at least one processor to:

communicate the code to a security module based on a determination that the code is in a writeable memory region.

7. An apparatus comprising:

a processor coupled to a memory; and

the memory storing executable instructions that when executed by the processor cause the processor to:

detect execution of a GetPC instruction sequence;

in response to detecting the execution of the GetPC instruction sequence, return to the Get PC instruction sequence a poison GetPC address in a GetPC address region on the memory instead of a current PC address, wherein the poison GetPC address is an identifiable invalid address;

determine whether self-modifying code is detected;

monitor, based on a determination that self-modifying code is detected, code as it executes to detect whether execution of the self-modifying code occurred at the poison GetPC address in the GetPC address region; and

based on a determination that the execution of the self-modifying code occurred at the poison GetPC address in the GetPC address region of the memory:

log an event; and

analyze the code for malware.

8. The apparatus of claim 7 , wherein the poison GetPC address causes a memory fault.

9. The apparatus of claim 7 , wherein the executable instructions that when executed by the processor further cause the processor to:

log the event based on a determination that a memory fault exception occurred during translation and the memory fault translation matches with the identifiable invalid address.

10. The apparatus of claim 7 , wherein the executable instructions that when executed by the processor further cause the processor to:

communicate the code to a security module based on a determination that the self-modifying code occurred at the poison GetPC address in the GetPC address region.

11. The apparatus of claim 7 , wherein the executable instructions that when executed by the processor further cause the processor to:

determine whether an exception occurred during a translation of the code; and

log an event based on a determination that the exception occurred at the identifiable invalid address.

12. The apparatus of claim 7 , wherein the executable instructions that when executed by the processor further cause the processor to:

communicate the code to a security module based on a determination that the code is in a writeable memory region.

13. A method comprising:

detecting execution of a GetPC instruction sequence;

in response to detecting the execution of the GetPC instruction sequence, returning to the GetPC instruction sequence a poison GetPC address in a GetPC address region instead of a current PC address, wherein the poison GetPC address is an identifiable invalid address;

determining whether self-modifying code is detected;

monitoring, based on a determination that self-modifying code is detected, code as it executes to detect whether execution of the self-modifying code occurred at the poison GetPC address in the GetPC address region; and

based on a determination that the execution of the self-modifying code occurred at the poison GetPC address in the GetPC address region:

logging an event; and

analyzing the code for malware.

14. The method of claim 13 , wherein the poison GetPC address causes a memory fault.

15. The method of claim 13 , further comprising:

logging the event based on a determination that a memory fault exception occurred during translation and the memory fault translation matches with the identifiable invalid address.

16. The method of claim 13 , further comprising:

communicating the code to a security module based on a determination that the self-modifying code occurred at the poison GetPC address in the GetPC address region.

17. The method of claim 13 , further comprising:

determining whether an exception occurred during a translation of the code; and

logging the event based on a determination that the exception occurred at the identifiable invalid address.

18. The at least one machine readable medium of claim 1 , wherein the self-modifying code includes a self-decrypting code sequence.

19. The apparatus of claim 7 , wherein the self-modifying code includes a self-decrypting code sequence.

20. The method of claim 13 , wherein the self-modifying code includes a self-decrypting code sequence.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE PATENT TITLES AND REMOVE DUPLICATES IN THE SCHEDULE PREVIOUSLY RECORDED AT REEL: 059354 FRAME: 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 23, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 060792/0307 →
SECURITY INTEREST Recorded Mar 3, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
Reel/Frame 059354/0335 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045056/0676 Recorded Mar 2, 2022
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 059354/0213 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045055/0786 Recorded Oct 26, 2020
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 054238/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045056 FRAME 0676. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 054206/0593 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045055 FRAME 786. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 055854/0047 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 045055/0786 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 045056/0676 →
CHANGE OF NAME AND ENTITY CONVERSION Recorded Aug 24, 2017
From: MCAFEE, INC.
To: MCAFEE, LLC
Reel/Frame 043665/0918 →