IP Library Granted Patent US 9,870,745
Granted Patent B2
US 9,870,745 · App. 14/867,417 · Granted Jan 16, 2018

Display device and driving circuit

Inventors: Tetsuya Kawamura (Hyogo, JP); Hironori Yasukawa (Hyogo, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G09G3/3648G02F1/1345G09G3/3611G02F1/136286G09G2300/0426G09G2300/0465G09G2310/0264G09G2310/0281G09G2310/08
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Quick Facts
Patent No.
US 9,870,745
App. No.
14/867,417
Granted
Jan 16, 2018
Kind
B2
Abstract

Provided is a display device, including: a driving circuit including a first output terminal group including at least one gate signal output terminal, and a second output terminal group including at least one source signal output terminal; and a plurality of gate lead-out lines configured to transmit a gate signal to a plurality of gate lines, in which each or the plurality of gate lines is electrically connected to at least one of the gate lead-out lines, and the first output terminal group is arranged between two adjacent second output terminal groups.

Claims (33)

1. A display device, comprising:

a plurality of gate lines extending in a first direction;

a plurality of source lines extending in a second direction different from the first direction;

a driving circuit comprising:

a first output terminal group comprising at least one gate signal output terminal configured to output a gate signal; and

a second output terminal group comprising at least one source signal output terminal configured to output a source signal; and

a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal output from the at least one gate signal output terminal to the plurality of gate lines,

wherein each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines,

the first output terminal group is arranged between two second output terminal groups adjacent to each other in the first direction,

the plurality of gate lead-out lines includes a first gate lead-out line and a second gate lead-out line that are electrically independent from each other,

the plurality of gate lines includes a first gate line and a second gate line,

the first gate lead-out line is electrically connected with the first gate line,

the second gate lead-out line is electrically connected with the second gate line, and

the first gate lead-out line is not electrically connected with the second gate line.

2. The display device according to claim 1 , further comprising a plurality of source lead-out lines configured to transmit the source signal output from the at least one source signal output terminal to the plurality of source lines,

wherein, outside a display region, the plurality of source lead-out lines and the plurality of gate lead-out lines are arranged so as to avoid intersecting with each other in plan view.

3. The display device according to claim 1 , wherein at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines.

4. The display device according to claim 1 , further comprising a plurality of gate bundled lines formed by bundling a predetermined number of the plurality of gate lead-out lines outside a display region,

wherein each of the plurality of gate bundled lines is electrically connected to each of a plurality of the gate signal output terminals, and is configured to transmit the gate signal output from each of the plurality of the gate signal output terminals to the predetermined number of the plurality of gate lead-out lines.

5. The display device according to claim 4 , wherein the each of the plurality of gate bundled lines is formed by bundling a plurality of adjacent gate lead-out lines outside the display region.

6. The display device according to claim 5 , further comprising a plurality of source lead-out lines configured to transmit the source signal output from the at least one source signal output terminal to the plurality of source lines,

wherein, outside the display region, the plurality of source lead-out lines and the plurality of gate bundled lines are arranged so as to avoid intersecting with each other in plan view.

7. The display device according to claim 1 , further comprising a first insulating film formed between the plurality of gate lines and the plurality of gate lead-out lines,

wherein the each of the plurality of gate lines and each of the plurality of gate lead-out lines are electrically connected to each other via a contact hole formed through the first insulating film.

8. The display device according to claim 1 ,

wherein each of the plurality of gate lead-out lines has a width that is equal to or less than a width of each of the plurality of source lines, and

wherein, inside a display region, the each of the plurality of gate lead-out lines and the each of the plurality of source lines overlap with each other in plan view.

9. The display device according to claim 7 , further comprising a second insulating film formed between the plurality of gate lines and the plurality of source lines,

wherein the first insulating film is formed on the plurality of gate lead-out lines,

wherein the plurality of gate lines are formed on the first insulating film,

wherein the second insulating film is formed on the plurality of gate lines, and

wherein the plurality of source lines are formed on the second insulating film.

10. The display device according to claim 1 , further comprising a transistor connected to a pixel electrode in a pixel region sectioned by adjacent two of the plurality of source lines, adjacent two of the plurality of gate lines, and four intersecting portions at which the adjacent two of the plurality of source lines and the adjacent two of the plurality of gate lines intersect with each other, wherein the transistor being arranged at one intersecting portion different from another intersecting portion at which a connecting portion formed between corresponding one of the plurality of gate lines and corresponding one of the plurality of gate lead-out lines is positioned.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2015
From: KAWAMURA, TETSUYA; YASUKAWA, HIRONORI
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 036816/0188 →
Priority Claims (1)
JP 2014-199437 · Sep 29, 2014 · national
Continuity (1)
Related Publication 20160093261A1 · Mar 31, 2016