IP Library Granted Patent US 9,812,468
Granted Patent B2
US 9,812,468 · App. 14/867,430 · Granted Nov 7, 2017

Display device including wider gate lead-out lines

Inventors: Tetsuya Kawamura (Hyogo, JP); Hironori Yasukawa (Hyogo, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
H01L27/124G02F1/13G09G3/3674G09G2300/0426G09G2310/0281
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Quick Facts
Patent No.
US 9,812,468
App. No.
14/867,430
Granted
Nov 7, 2017
Kind
B2
Abstract

Provided is a display device, including: a plurality of gate lines extending in a first direction; a plurality of source lines extending in a second direction; a gate driver configured to output a gate signal; and a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal to the plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines, and at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines.

Claims (29)

1. A display device, comprising:

a plurality of gate lines extending in a first direction;

a plurality of source lines extending in a second direction different from the first direction;

a gate driver configured to output a gate signal; and

a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal output from the gate driver to the plurality of gate lines,

wherein each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines, and

wherein at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines,

wherein the plurality of gate lead-out lines includes a first gate lead-out line and a second gate lead-out line, and the first gate lead-out line is not electrically connected with the second gate lead-out line,

wherein the plurality of gate lines includes a first gate line and a second gate line, the first gate lead-out line is electrically connected with the first gate line, and the second gate lead-out line is electrically connected with the second gate line, and

wherein the first gate lead-out line is not electrically connected with the second gate line.

2. The display device according to claim 1 , further comprising a first insulating film formed between the plurality of gate lines and the plurality of gate lead-out lines,

wherein the each of the plurality of gate lines and each of the plurality of gate lead-out lines are electrically connected to each other via a contact hole formed through the first insulating film.

3. The display device according to claim 1 ,

wherein each of the plurality of gate lead-out lines has a width that is equal to or less than a width of each of the plurality of source lines, and

wherein, in plan view, the each of the plurality of gate lead-out lines and the each of the plurality of source lines overlap with each other.

4. The display device according to claim 2 , further comprising a second insulating film formed between the plurality of gate lines and the plurality of source lines,

wherein the first insulating film is formed on the plurality of gate lead-out lines,

wherein the plurality of gate lines are formed on the first insulating film,

wherein the second insulating film is formed on the plurality of gate lines, and

wherein the plurality of source lines are formed on the second insulating film.

5. The display device according to claim 1 , wherein a number of the plurality of gate lead-out lines electrically connected to corresponding one of the plurality of gate lines, which is arranged at a position far from a location where the gate driver is arranged, is larger than a number of the plurality of gate lead-out lines electrically connected to corresponding one of the plurality of gate lines, which is arranged at a position close to the location where the gate driver is arranged.

6. The display device according to claim 1 , wherein a connecting portion formed between a first gate line, which is arranged at a position far from a location where the gate driver is arranged, and corresponding one of the plurality of gate lead-out lines is arranged on a lateral side of a display region with respect to a connecting portion formed between a second gate line, which is arranged at a position closer to the location where the gate driver is arranged than the first gate line, and corresponding one of the plurality of gate lead-out lines.

7. The display device according to claim 1 , further comprising a transistor connected to a pixel electrode in a pixel region sectioned by adjacent two of the plurality of source lines, adjacent two of the plurality of gate lines, and four intersecting portions at which the adjacent two of the plurality of source lines and the adjacent two of the plurality of gate lines intersect with each other, wherein the transistor being arranged at one intersecting portion different from another intersecting portion at which a connecting portion formed between corresponding one of the plurality of gate lines and corresponding one of the plurality of gate lead-out lines is positioned.

8. The display device according to claim 1 , further comprising a plurality of bundled lines each formed by bundling a predetermined number of the plurality of gate lead-out lines outside of a display region,

wherein each of the plurality of bundled lines is configured to transmit the gate signal output from the gate driver to the predetermined number of the plurality of gate lead-out lines.

9. The display device according to claim 8 , wherein the each of the plurality of bundled lines is formed by bundling a plurality of adjacent gate lead-out lines outside of the display region.

10. The display device according to claim 1 , wherein an interval between two of a plurality of connecting portions formed between one of the plurality of gate lines and a plurality of the gate lead-out lines electrically connected thereto is equal to an interval between two of a plurality of connecting portions formed between another of the plurality of gate lines and a plurality of the gate lead-out lines electrically connected thereto.

11. The display device according to claim 1 , wherein the gate driver is configured to output the gate signal to the plurality of gate lead-out lines electrically connected to the same gate line within the same horizontal scanning period.

12. The display device according to claim 1 , wherein the each of the plurality of gate lines is electrically connected to a plurality of the gate lead-out lines adjacent to each other in the first direction.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2015
From: KAWAMURA, TETSUYA; YASUKAWA, HIRONORI
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 036816/0190 →
Priority Claims (1)
JP 2014-199436 · Sep 29, 2014 · national
Continuity (1)
Related Publication 20160093640A1 · Mar 31, 2016