Contacts for highly scaled transistors

1. A method of forming a contact in a vertical gate-all-around (VGAA) device, comprising:

receiving a VGAA device, the VGAA device having:

a substrate;

a first source/drain (S/D) region over the substrate;

an isolation structure over the substrate and surrounding the first S/D region;

a channel over the first S/D region;

a second S/D region over the channel;

a gate wrapping around the channel; and

a dielectric layer over the isolation structure and the first S/D region;

etching the dielectric layer and the isolation structure to form an opening, wherein the opening exposes at least two sides of the first S/D region;

forming a first contact layer in the opening, wherein the first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region; and

forming a second contact layer in the opening over the first contact layer.

2. The method of claim 1 , wherein the first contact layer includes one of InAs, InGaAs, InP, and Ge.

3. The method of claim 1 , wherein the first contact layer includes a semiconductor-metal alloy.

4. The method of claim 1 , wherein the opening exposes a top surface and two sidewall surfaces of the first S/D region.

5. A method of forming a contact in a multi-gate semiconductor device, comprising:

receiving a multi-gate semiconductor device having:

a substrate;

first and second source/drain (S/D) regions;

a channel between the first and second S/D regions;

a gate engaging the channel; and

a dielectric layer over the first S/D region;

etching the dielectric layer to form an opening, wherein the opening exposes at least two sides of the first S/D region;

forming a first contact layer in the opening, wherein the first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region; and

forming a second contact layer in the opening over the first contact layer.

6. The method of claim 5 , wherein the first contact layer includes one of III-V semiconductors.

7. The method of claim 5 , wherein:

the first contact layer includes a material selected from the group consisting of titanium, cobalt, nickel, nickel cobalt, and germanium.

8. The method of claim 5 , wherein the multi-gate semiconductor device further includes a contact etch stop (CES) layer between the dielectric layer and the first S/D region, wherein the etching of the dielectric layer includes:

etching the CES layer within the opening to expose the at least two sides of the first S/D region.

9. The method of claim 5 , wherein the first S/D region is a fin structure having opposing sidewall surfaces.

10. The method of claim 9 , wherein forming the first contact layer in the opening includes forming the first contact layer directly on the opposing sidewall surfaces such that the first contact layer physically contacts the opposing sidewall surfaces.

11. The method of claim 5 , further comprising:

epitaxially growing a semiconductor material on the first S/D region to form a diamond shaped S/D feature, the diamond shaped S/D feature having a first side, a second side, a third side, and a fourth side, and

wherein forming the first contact layer in the opening includes forming the first contact layer directly on the first side, the second side, the third side, and the fourth side.

12. The method of claim 5 , further comprising:

forming a semiconductor material on the first S/D region to form a multi-sided S/D feature, the multi-sided S/D feature having a first side surface and a second side surface,

wherein forming the first contact layer in the opening includes forming the first contact layer directly on the first side surface without forming the first contact layer directly on the second side surface.

13. A method comprising:

forming a gate stack over a substrate;

forming a source/drain feature over the substrate, the source/drain feature having a first side surface, a second side surface, and a third side surface;

forming a dielectric layer over the source/drain feature and the gate stack;

forming a trench through the dielectric layer to expose at least the first side surface, the second side surface, and third side surface;

forming a first contact layer in the trench such that the first contact layer physically contacts the first side surface, the second side surface, and third side surface; and

forming a second contact layer in the trench over the first contact layer.

14. The method of claim 13 , wherein after forming the first contact layer in the trench, at least one of the first side surface, the second side surface, and the third side surface includes a portion that physically contacts the dielectric layer.

15. The method of claim 13 , wherein the first side surface intersects the second side surface, and

wherein the third side surface intersects the second side surface without intersecting the first side surface.

16. The method of claim 13 , further comprising forming a fin structure over the substrate, and

wherein forming the source/drain feature over the substrate includes forming the source/drain feature directly on the fin structure.

17. The method of claim 16 , wherein the first side surface and the second side surface directly interface with the fin structure.

18. The method of claim 13 , wherein the first contact layer includes a III-V semiconductor material layer, and

wherein the second contact layer includes a metallic material layer.

19. The method of claim 13 , further comprising forming another source/drain feature over the substrate, and

wherein forming the trench through the dielectric layer further exposes the another source/drain feature, and

wherein forming the first contact layer in the trench further includes forming the first contact layer directly on the another source/drain feature such that the first contact layer physically contacts the another source/drain feature, the first contact layer extending continuously from the source/drain feature to the another source/drain feature.

20. The method of claim 19 , wherein the source/drain feature physically contacts the another source/drain feature.