IP Library Patent Application 14876595
Patent Application
App. No. 14/876,595

METHOD FOR PARSING NETWORK PACKETS HAVING FUTURE DEFINED TAGS

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Quick Facts
Patent No.
US None
App. No.
14/876,595
Abstract

Methods and systems are provided for enabling existing or legacy network devices to handle packets defined in accordance with future-defined standards, without having to be re-configured to be compatible with these standards. A transmitting network device may generate packets, and may set in the packets indication fields (e.g., tag header type fields) to indicate when particular fields (e.g., tag header fields) are inserted into the packets, including unknown or newly-defined fields. The indication fields may enable a receiving device to handle the packets by skipping, when necessary, over these fields (e.g., including the unknown or newly-defined fields). The indication fields may, for example, identify for each packet a remaining portion to jump to without reading the inserted fields.

Claims (40)

1 - 17 . (canceled)

18 . A method, comprising:

generating a packet;

inserting a tag header in the packet;

setting a tag header type in a first portion of the packet to:

indicate that the tag header is inserted; and

identify a remaining portion of the packet, such that to enable reading the remaining portion of the packet without reading the tag header inserted in the packet.

19 . The method of claim 18 , comprising, when an additional tag header is inserted in the packet, setting an additional tag header type in a second portion of the packet to indicate that the additional tag header is inserted;

wherein the additional tag header type is set to identify a second remaining portion of the packet, such that to enable reading the second remaining portion of the packet without reading the additional tag header inserted in the packet.

20 . The method of claim 18 , comprising setting the tag header type based on one or more tag header lengths, associated with corresponding one or more tag header types.

21 . The method of claim 18 , comprising generating the packet such that to enable controlling processing of the packet at a receiving device.

22 . The method of claim 21 , comprising setting a field in the remaining portion of the packet to enable controlling the processing of the packet at the receiving device.

23 . The method of claim 22 , wherein the field comprises an indication of which type of network frame is encapsulated in the packet.

24 . The method of claim 21 , wherein controlling the processing of the packet comprises offloading processing of the packet to a particular component of the receiving device, the particular component comprising hardware or software client.

25 . A system, comprising:

one or more circuits for use in a device, the one or more circuits are operable to:

generate a packet;

insert a tag header in the packet; and

set a tag header type in a first portion of the packet to:

indicate that the tag header is inserted; and

identify a remaining portion of the packet, such that to enable reading the remaining portion of the packet without reading the tag header inserted in the packet.

26 . The system of claim 25 , wherein the one or more circuits are operable to, when an additional tag header is inserted in the packet set an additional tag header type in a second portion of the packet to indicate that the additional tag header is inserted;

wherein the additional tag header type is set to identify a second remaining portion of the packet, such that to enable reading the second remaining portion of the packet without reading the additional tag header inserted in the packet.

27 . The system of claim 25 , wherein the one or more circuits are operable to set the tag header type based on one or more tag header lengths, associated with corresponding one or more tag header types.

28 . The system of claim 25 , wherein the identified remaining portion of the packet includes an indication of which type of network frame is encapsulated in the packet.

29 . The system of claim 25 , wherein the device is incorporated into a host bus adapter (HBA).

30 . The system of claim 25 , wherein the device is incorporated into a converged network adapter (CNA).

31 . The system of claim 25 , wherein the device is incorporated into a target channel adapter (TCA).

32 . The system of claim 25 , wherein the device is a network interface card (NIC).

33 . A non-transitory computer-readable storage medium comprising processor-executable instructions, said instructions, while executed, causing a processor to:

generate a packet;

insert a tag header in the packet;

set a tag header type in a first portion of the packet to:

indicate that the tag header is inserted; and

identify a remaining portion of the packet, such that to enable reading the remaining portion of the packet without reading the tag header inserted in the packet.

34 . The non-transitory computer-readable storage medium of claim 33 , wherein said instructions, while executed, cause the processor to, when an additional tag header is inserted in the packet, set an additional tag header type in a second portion of the packet to indicate that the additional tag header is inserted;

wherein the additional tag header type is set to identify a second remaining portion of the packet, such that to enable reading the second remaining portion of the packet without reading the additional tag header inserted in the packet.

35 . The non-transitory computer-readable storage medium of claim 33 , wherein said instructions, while executed, cause the processor to set a field in the remaining portion of the packet to enable controlling the processing of the packet at a receiving device.

36 . The non-transitory computer-readable storage medium of claim 33 , wherein the field comprises an indication of which type of network frame is encapsulated in the packet.

37 . The non-transitory computer-readable storage medium of claim 33 , wherein controlling the processing of the packet comprises offloading processing of the packet to a particular component of the receiving device.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2016
From: EMULEX CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 039235/0317 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2015
From: EMULEX DESIGN AND MANUFCTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 036744/0246 →