IP Library › Patent Application 14876787

Patent Application

App. No. 14/876,787

Manufacturing Method of Semiconductor Device

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Quick Facts

Patent No.: US None
App. No.: 14/876,787

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Abstract

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Claims (67)

1 - 13 . (canceled)

14 . A semiconductor device, comprising:

a semiconductor chip including a main surface, and a pad formed over the main surface;

a first insulating layer formed over the main surface of the semiconductor chip;

a wiring formed over the first insulating layer; and

a bump electrode formed on a part of the wiring,

wherein the pad is located closer than the bump electrode to a peripheral portion of the semiconductor chip,

wherein a probe mark is formed in a first area of a surface of the pad,

wherein the first insulating layer has an opening,

wherein a second area of the surface of the pad is exposed from the opening of the first insulating layer,

wherein the second area is located closer than the first area to a central portion of the semiconductor chip,

wherein the wiring is connected with the pad in the second area but not in the first area, and

wherein the wiring is led out from the second area toward the central portion of the semiconductor chip such that the wiring does not overlap with the probe mark in a plan view.

15 . The semiconductor device according to claim 14 ,

wherein the first area of the surface of the pad is covered with the first insulating layer.

16 . The semiconductor device according to claim 14 ,

wherein a second insulating layer is formed over the main surface,

wherein the second insulating layer has an opening,

wherein the surface of the pad is exposed from the opening of the second insulating layer, and

wherein the first insulating layer is formed on the second insulating layer.

17 . The semiconductor device according to claim 14 ,

wherein a third insulating layer is formed on the first insulating layer,

wherein the third insulating layer has an opening,

wherein the part of the wiring is exposed from the opening of the third insulating layer.

18 . The semiconductor device according to claim 17 ,

wherein a portion of the bump electrode is located inside the opening of the third insulating layer.

19 . The semiconductor device according to claim 14 ,

wherein the wiring is connected with the pad via a seed layer.

20 . The semiconductor device according to claim 19 ,

wherein the seed layer is extended to a surface of the first insulating layer,

wherein the seed layer is connected with the pad in the second area but not in the first area, and

wherein the wiring is formed on the first insulating layer via the seed layer.

21 . The semiconductor device according to claim 14 ,

wherein the probe mark is a damage mark formed by contacting a probe pin with the surface of the pad in a probe test.

22 . A semiconductor device, comprising: