IP Library Granted Patent US 9,501,089
Granted Patent B2
US 9,501,089 · App. 14/879,905 · Granted Nov 22, 2016

Induction-coupled clock distribution for an integrated circuit

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Quick Facts
Patent No.
US 9,501,089
App. No.
14/879,905
Granted
Nov 22, 2016
Kind
B2
Abstract

An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

Claims (34)

1. An integrated circuit package, comprising:

a transmission module coupled to a main clock line;

a semiconductor die;

a clock reception module disposed on the semiconductor die and inductively coupled to the transmission module, the clock reception module configured to generate a clocking signal on a clock output line; and

an electronic circuit disposed on the semiconductor die and coupled to the clock output line of the clock reception module, the electronic circuit comprising at least one clocked element, and configured to operate synchronously with the clocking signal received through the clock output line of the clock reception module.

2. The integrated circuit package of claim 1 , wherein the transmission module comprises a transmission coil and the clock reception module comprises a reception coil.

3. The integrated circuit package of claim 2 , wherein the transmission coil is disposed such that an area within the transmission coil includes the reception coil.

4. The integrated circuit package of claim 2 , wherein a connecting area is provided between two portions of the transmission coil to provide a connection to the main clock line.

5. The integrated circuit package of claim 2 , wherein the transmission module is positioned in a plane parallel to and spaced away from the semiconductor die.

6. The integrated circuit package of claim 5 , wherein the reception coil is disposed directly under the transmission coil.

7. The integrated circuit package of claim 5 , further comprising a supporting case configured to enclose the semiconductor die, wherein the transmission module is within the supporting case.

8. The integrated circuit package of claim 5 , further comprising a supporting case configured to enclose the semiconductor die, wherein the transmission module is disposed on the supporting case.

9. The integrated circuit package of claim 5 , further comprising a supporting case configured to enclose the semiconductor die wherein the transmission module is disposed on an interposer attached to the supporting case.

10. The integrated circuit package of claim 2 , wherein the transmission coil is positioned in a same plane as the reception coil.

11. The integrated circuit package of claim 1 , wherein the transmission module is external to the integrated circuit package.

12. The integrated circuit package of claim 1 , wherein the transmission module comprises a transmission coil, and the clock reception module comprises a resonant circuit,

wherein the inductive coupling of the transmission module and the clock reception module comprises an inductive coupling of the transmission coil and the resonant circuit, and

wherein the clock reception module is configured to generate the clocking signal based on a resonance of the resonant circuit.

13. An integrated circuit package, comprising:

a semiconductor die;

a transmission module coupled to a main clock line;

a plurality of clock reception modules inductively coupled to the transmission module and disposed on the semiconductor die, each clock reception module comprising a clock output line; and

a plurality of electronic circuits disposed on the semiconductor die, each electronic circuit coupled to the clock output line of a corresponding clock reception module of the plurality of clock reception modules, each electronic circuit comprising at least one clocked element and configured to operate synchronously with a clocking signal received through the corresponding clock output line.

14. The integrated circuit package of claim 13 , wherein the transmission module comprises a transmission coil and each of the plurality of clock reception modules comprises a reception coil.

15. The integrated circuit package of claim 14 , wherein the transmission coil is disposed such that an area within the transmission coil includes the reception coil comprised by each of the plurality of clock reception modules.

16. The integrated circuit package of claim 14 , wherein the transmission module is positioned in a plane parallel to and spaced from the semiconductor die.

17. An integrated circuit package, comprising:

a semiconductor die;

a transmission module disposed on the semiconductor die and coupled to a main clock line;

a clock reception module inductively coupled to the transmission module, the clock reception module configured to generate a clocking signal on a clock output line,

wherein an electronic circuit is coupled to the clock output line of the clock reception module and configured to operate synchronously with the clocking signal received through the clock output line of the clock reception module.

18. The integrated circuit package of claim 17 , wherein the transmission module comprises a transmission coil and the clock reception module comprises a reception coil.

19. The integrated circuit package of claim 18 , wherein the reception coil is disposed on the integrated circuit package.

20. The integrated circuit package of claim 18 , wherein the reception coil is external to the integrated circuit package.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2015
From: CHANG, DAVID; HUKKOO, AJAT
To: BROADCOM CORPORATION
Reel/Frame 036796/0988 →