Method and apparatus for sensing multiple voltage values from a single terminal of a power converter controller

1. A controller for a power converter, comprising:

a switching control coupled to switch a power switch of the power converter to regulate an output of the power converter; and

a sensor coupled to receive a signal from a single terminal of the controller, wherein the signal from the single terminal is representative of a line input voltage of the power converter during at least a portion of an on time of the power switch, wherein the signal from the single terminal is representative of an output voltage of the power converter during at least a portion of an off time of the power switch, and wherein the switching control is responsive to an output of the sensor, the sensor further comprising:

a first current source;

an internal voltage supply coupled to the first current source; and

a buffer circuit coupled to receive the signal from the single terminal, wherein the first current source is coupled to supply a first current to the buffer circuit.

2. The controller of claim 1 , wherein the buffer circuit comprises a first transistor and a second transistor, wherein a gate of the second transistor is coupled to a drain of the second transistor.

3. The controller of claim 2 , wherein the sensor further comprises:

a second current source, wherein the second current source is coupled to sink a second current from the second transistor; and

a third transistor coupled between the gate of the second transistor and a voltage terminal.

4. The controller of claim 3 , wherein a voltage at a gate of the first transistor is representative of the line input voltage of the power converter during said at least the portion of the on time of the power switch.

5. The controller of claim 4 , wherein a gate of the third transistor is coupled to receive a first clock signal, wherein the first clock signal is a pulsed signal that pulses after a first delay time after the power switch is turned off.

6. The controller of claim 5 , wherein the sensor further comprises:

a third current source; and

a fourth transistor, wherein the internal voltage supply is coupled to the third current source, and wherein the third current source is further coupled to supply a third current to the fourth transistor.

7. The controller of claim 6 , wherein the sensor further comprises a fifth transistor, wherein a gate of the fourth transistor is coupled to a drain of the fourth transistor and a gate of the fifth transistor.

8. The controller of claim 7 , wherein the sensor further comprises a sixth transistor coupled between the internal voltage supply and the fifth transistor, wherein a gate of the sixth transistor is coupled to a drain of the sixth transistor.

9. The controller of claim 8 , wherein the sensor further comprises:

a seventh transistor; and

an eighth transistor, wherein the seventh transistor is coupled between a gate of the sixth transistor and a gate of the eighth transistor.

10. The controller of claim 9 , wherein the sensor further comprises an inverter, wherein an output of the inverter is coupled to a gate of the seventh transistor, and wherein an input of the inverter is coupled to receive a second clock signal.

11. The controller of claim 10 , wherein the sensor further comprises:

a first capacitor coupled to the voltage terminal, wherein a voltage at the voltage terminal is representative of the output voltage of the power converter; and

a second capacitor coupled between the internal voltage supply and a gate of the eighth transistor.

12. The controller of claim 11 , wherein the first capacitor is coupled to be charged or discharged for a time during which a pulse of the first clock signal is high.

13. The controller of claim 12 , wherein the first capacitor is coupled to be charged or discharged to a voltage at the single terminal when the first clock signal is high.

14. The controller of claim 13 , wherein the output of the sensor is coupled to be adjusted to the voltage at the single terminal when the first clock signal is high.

15. The controller of claim 10 , wherein the second clock signal is a pulsed signal that pulses after a second time delay after the power switch is turned on.

16. The controller of claim 15 , wherein the second capacitor is coupled to be charged or discharged for a time during which a pulse of the second clock signal is high.

17. The controller of claim 11 , wherein a voltage at the gate of the eighth transistor is coupled to be adjusted to be equal to a voltage at the gate of the sixth transistor when the second clock signal is high.