IP Library Granted Patent US 9,477,413
Granted Patent B2
US 9,477,413 · App. 14/885,018 · Granted Oct 25, 2016

System and method for managing access requests to a memory storage subsystem

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Quick Facts
Patent No.
US 9,477,413
App. No.
14/885,018
Granted
Oct 25, 2016
Kind
B2
Abstract

Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution. In embodiments, the execution manager traverses a list of received requests for memory access and dispatches commands for execution. In embodiments, if a request is directed to memory units which have reached a threshold for outstanding requests, the request may be skipped so that other requests can be dispatched for memory units which have not yet reached the threshold.

Claims (30)

1. A storage subsystem, comprising:

a controller;

a non-volatile solid-state memory array, the non-volatile solid-state memory array including a plurality of memory units in electrical contact with the controller;

wherein the controller is configured to:

receive a plurality of requests for access to the non-volatile solid-state memory array,

process each received request for execution and associate each received request with a memory unit in the plurality of memory units;

maintain a list of the plurality of received requests;

maintain a record of a number of outstanding requests associated with each of the plurality of memory units;

selectively send a request from the list of received requests to the memory unit associated with the request;

wherein a request is selected based at least in part on determining if a number of outstanding requests associated with a memory unit associated with the request is less than an outstanding request threshold;

traverse the list of the plurality of received requests,

skip a request if it is determined that the number of outstanding requests associated with a memory unit associated with the request is more than an outstanding request threshold, and

return to a reset traversal point on the list to re-evaluate the skipped requests after a condition has been reached.

2. The storage subsystem of claim 1 , wherein the condition is based at least partially on one of: a number of requests that have been skipped, a number of requests that have been sent, the traversing reaching the end of the list of received requests, the traversing reaching the end of a snapshot of the list of received requests, and a completion of a request associated with a memory unit which has been skipped.

3. The storage subsystem of claim 1 , wherein the received plurality of requests for access are not configured for execution on the memory units and the controller is further configured to translate the requests for access to commands executable on the memory units prior to sending to the memory units.

4. The storage subsystem of claim 1 , wherein the received plurality of requests for access are configured for execution on the memory units without translation by the controller.

5. The storage subsystem of claim 1 , wherein the received plurality of requests for access are configured for execution on the memory units without modification by the controller.

6. The storage subsystem of claim 1 , wherein each memory unit comprises a die.

7. The storage subsystem of claim 1 , wherein each memory unit is accessible via an associated data channel.

8. A method of executing memory access requests on a plurality of memory units in a storage subsystem, the method comprising:

receiving, at a controller, a plurality of requests for memory access;

preparing, at the controller, the plurality of requests for execution and associating each request with a memory unit in the plurality of memory units;

maintaining, by the controller, a list of the plurality of received requests;

maintaining, by the controller, a record of a number of outstanding requests associated with each of the plurality of memory units; and

selectively sending, by the controller, a request from the list of requests to the memory unit associated with the requests, wherein a request is selected based at least in part on determining if a number of outstanding requests associated with a memory unit associated with the request is less than an outstanding request threshold;

traversing, by the controller, the list of the plurality of requests;

skipping, by the controller, a request if the number of outstanding requests associated with a memory unit associated with the request is more than an outstanding request threshold; and

returning, by the controller, to a traversal point on the list to re-evaluate the skipped requests after a condition has been reached.

9. The method of claim 8 , wherein preparing the plurality of requests includes translating the requests for execution on the plurality of memory units in the storage subsystem.

10. The method of claim 8 , wherein the condition is based at least partially on one of: a number of requests that have been skipped, a number of requests that have been sent, the traversing reaching the end of the list of received requests, the traversing reaching the end of snapshot of the list of received requests, and a completion of a request associated with memory unit which has been skipped.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: PALISADE TECHNOLOGIES, LLP
Reel/Frame 068301/0240 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2016
From: PHAN, LAN D.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 039775/0609 →