METHOD AND SYSTEM FOR GAN VERTICAL JFET UTILIZING A REGROWN GATE
A vertical field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
1 . A method for fabricating a semiconductor device, the method comprising:
providing a III-nitride substrate;
forming a first III-nitride epitaxial layer coupled to the III-nitride substrate, wherein the first III-nitride epitaxial layer is characterized by a first dopant concentration;
forming a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial layer, wherein the second III-nitride epitaxial layer has a second dopant concentration of the same type and less than or equal to the first dopant concentration;
forming a third III-nitride epitaxial layer coupled to the second III-nitride epitaxial layer, wherein the third III-nitride epitaxial layer has a third dopant concentration of the same type and greater than the first dopant concentration; and
forming a fourth III-nitride epitaxial layer coupled to the second III-nitride epitaxial layer, wherein, while the fourth III-nitride epitaxial layer is formed, the third III-nitride epitaxial layer is protected such that the fourth III-nitride epitaxial layer does not grow from the third III-nitride epitaxial layer while the fourth III-nitride epitaxial layer is grown from both the preexisting first and second III-nitride epitaxial layers, and wherein the fourth III-nitride epitaxial layer is of an opposite type from the first III-nitride epitaxial layer.
2 . The method of claim 1 , wherein the first III-nitride layer comprises an n-type GaN epitaxial layer.
3 . The method of claim 1 , wherein a thickness of the first III-nitride epitaxial layer is between about 1 μm and about 100 μm.
4 . The method of claim 3 , wherein the thickness is between about 10 μm and 80 μm.
5 . The method of claim 1 , wherein the first III-nitride epitaxial layer is an n-type layer and the epitaxial layer of the opposite type is a p-type layer.
6 . The method of claim 1 , wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform as a function of thickness.
7 . The method of claim 1 , further comprising:
forming a first metallic structure electrically coupled to the III-nitride substrate;
forming a second metallic structure electrically coupled to the epitaxial layer of the opposite type; and
forming a third metallic structure electrically coupled to the third III-nitride epitaxial layer.
8 . The method of claim 1 , further comprising:
removing at least a portion of the third III-nitride epitaxial layer and at least a portion of the second III-nitride epitaxial layer.
9 . A method for fabricating a semiconductor device, the method comprising:
providing a substrate;
forming a first epitaxial layer coupled to the substrate;
forming a second epitaxial layer coupled to the first epitaxial layer;
forming a third epitaxial layer coupled to the second epitaxial layer, wherein the third epitaxial layer is of the same type as the first and second epitaxial layers; and
forming a fourth epitaxial layer coupled to the first and second epitaxial layers, wherein, while the fourth epitaxial layer is formed, the third epitaxial layer is protected such that the fourth epitaxial layer does not grow from the third epitaxial layer while the fourth epitaxial layer is grown from both the preexisting first and second epitaxial layers, and wherein the fourth epitaxial layer is of an opposite type from the first, second, and third epitaxial layers.
10 . The method of claim 1 , wherein the first layer comprises an n-type GaN epitaxial layer.
11 . The method of claim 1 , wherein a thickness of the first epitaxial layer is between about 1 μm and about 100 μm.
12 . The method of claim 3 , wherein the thickness is between about 10 μm and 80 μm.
13 . The method of claim 1 , wherein the first epitaxial layer is an n-type layer and the epitaxial layer of the opposite type is a p-type layer.
14 . The method of claim 1 , wherein at least a dopant concentration of at least one of the first, second, and third epitaxial layers is non-uniform as a function of thickness.
15 . The method of claim 1 , further comprising:
forming a first metallic structure electrically coupled to the substrate;
forming a second metallic structure electrically coupled to the fourth epitaxial layer; and
forming a third metallic structure electrically coupled to the third epitaxial layer.
16 . The method of claim 1 , further comprising:
removing at least a portion of the third epitaxial layer and at least a portion of the second epitaxial layer.