Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method
A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.
1. A method, comprising:
forming a support structure including an insulating layer;
forming a semiconductor layer over the insulating layer;
removing at least a portion of the insulating layer to form a cavity under the semiconductor layer;
growing an epitaxial layer of semiconductor material on said semiconductor layer;
forming an opening extending through said epitaxial layer of semiconductor material at a position where a transistor gate is to be located to provide, from said epitaxial layer of semiconductor material, a source epitaxial region on one side of said opening and a drain epitaxial region on an opposite side of said opening;
after forming said cavity and said opening:
applying an anneal temperature to both the source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region to form a transistor source region from the source epitaxial region and the first portion, said transistor source region having a bottom surface at said cavity; and
applying an anneal temperature to both the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region to form a transistor drain region from the drain epitaxial region and the second portion, said transistor source region having a bottom surface at said cavity;
wherein a third portion of the semiconductor layer between the transistor source region and transistor drain region and over said cavity forms a transistor channel region; and
forming a transistor gate electrode in said opening above the transistor channel region.
2. The method of claim 1 , further comprising forming trench isolations to delimit an active region of said semiconductor layer.
3. The method of claim 1 , wherein the semiconductor layer is an upper semiconductor layer of a silicon on insulator (SOI) substrate.
4. The method of claim 1 , wherein forming the support structure comprises:
forming a lower semiconductor layer; and
forming the insulating layer on the lower semiconductor layer.
5. The method of claim 4 , wherein the semiconductor layer and lower semiconductor layer are made of a same semiconductor material.
6. The method of claim 5 , wherein the epitaxial layer is made of said same semiconductor material.
7. The method of claim 6 , wherein the semiconductor material is selected from the group consisting of a silicon-germanium material and an indium-gallium-arsenic material.
8. The method of claim 4 , wherein said lower semiconductor is a stress released semiconductor layer layer.
9. The method of claim 4 , further comprising:
forming a stress released semiconductor layer;
recessing a portion of said stress released semiconductor layer; and
wherein the semiconductor layer, the insulating layer and the lower semiconductor layer are formed in the recessed portion of said stress released semiconductor layer.
10. The method of claim 1 , wherein forming the opening comprises:
forming a dielectric layer over the epitaxial layer of semiconductor material;
forming a first opening extending through the dielectric layer at the position where the gate is to be located;
forming sidewall spacers on side walls of the first opening to define a second opening; and
extending the second opening through said epitaxial layer of semiconductor material to form said opening.
11. The method of claim 1 , wherein forming the opening comprises:
forming a sacrificial layer over the epitaxial layer of semiconductor material;
patterning the sacrificial layer to define a dummy gate at the position where the gate is to be located;
forming sidewall spacers on side walls of the dummy gate;
removing the dummy gate between the sidewall spacers to define a first opening; and
extending the first opening through said epitaxial layer of semiconductor material to form said opening.
12. The method of claim 1 , further comprising forming sidewall spacers on side walls of the opening and before performing said steps of applying the anneal temperature.
13. The method of claim 1 , wherein forming the transistor gate electrode comprises:
depositing a dielectric layer in the opening;
depositing a metal liner on the dielectric layer; and
filling said opening with a metal material.
14. The method of claim 1 , wherein the steps of applying the anneal temperature comprise performing a laser annealing of the epitaxial regions and underlying portions of the semiconductor layer.
15. A method, comprising:
forming an upper semiconductor layer over a lower semiconductor layer with an insulating layer positioned between the upper semiconductor layer and the lower semiconductor layer;
removing material of the insulating layer to form a cavity under the upper semiconductor layer;
growing an epitaxial layer of semiconductor material on the upper semiconductor layer;
forming an opening in said epitaxial layer of semiconductor material to define a source epitaxial region and a drain epitaxial region separated by said opening, said source epitaxial region overlying a source substrate region of the upper semiconductor layer and said drain epitaxial region overlying a drain substrate region of the upper semiconductor layer;
after said cavity and said opening have been formed, then:
simultaneously annealing both the source epitaxial region and source substrate region through to the cavity to form a transistor source region from the source epitaxial region and source substrate region; and
simultaneously annealing both the drain epitaxial region and drain substrate region through to the cavity to form a transistor drain region from the drain epitaxial region and drain substrate region;
wherein a portion of the semiconductor substrate layer between the source and drain substrate regions forms a transistor channel region with said cavity extending under said transistor channel region; and
forming a transistor gate electrode in said opening above the transistor channel region.
16. The method of claim 15 , wherein the steps of simultaneously annealing comprise performing a laser annealing.
17. The method of claim 15 , wherein forming the opening comprises:
forming a dielectric layer over the epitaxial layer of semiconductor material;
forming a first opening extending through the dielectric layer;
forming sidewall spacers on side walls of the first opening to define a second opening; and
extending the second opening through said epitaxial layer of semiconductor material to form said opening.
18. The method of claim 15 , wherein forming the opening comprises:
forming a sacrificial layer over the epitaxial layer of semiconductor material;
patterning the sacrificial layer to define a dummy gate;
forming sidewall spacers on side walls of the dummy gate;
removing the dummy gate between the sidewall spacers to define a first opening; and
extending the first opening through said epitaxial layer of semiconductor material to form said opening.
19. The method of claim 15 , further comprising forming sidewall spacers on side walls of the opening and before performing said steps of simultaneously annealing.
20. The method of claim 15 , wherein forming the transistor gate electrode comprises:
depositing a dielectric layer in the opening;
depositing a metal liner on the dielectric layer; and
filling said opening with a metal material.
21. A method, comprising:
growing an epitaxial layer of semiconductor material on a semiconductor layer which overlies an insulating layer supported by a substrate;
forming trench isolations in the semiconductor layer to define an active region;
removing the insulating layer within the active region to provide a cavity under the semiconductor layer;
forming an opening in said epitaxial layer of semiconductor material to define a source epitaxial region and a drain epitaxial region separated by said opening, said source epitaxial region overlying a source substrate region of the semiconductor substrate layer and said drain epitaxial region overlying a drain substrate region of the semiconductor substrate layer;
annealing to combine both the source epitaxial region and source substrate region into a transistor source region over said cavity;
annealing to combine both the drain epitaxial region and drain substrate region into a transistor drain region over said cavity;
wherein a portion of the semiconductor substrate layer between the source and drain substrate regions forms a transistor channel region over said cavity; and
forming a transistor gate electrode in said opening above the transistor channel region.
22. The method of claim 21 , wherein forming the opening comprises:
forming a dielectric layer over the epitaxial layer of semiconductor material;
forming a first opening extending through the dielectric layer;
forming sidewall spacers on side walls of the first opening to define a second opening; and
extending the second opening through said epitaxial layer of semiconductor material to form said opening.
23. The method of claim 21 , wherein forming the opening comprises:
forming a sacrificial layer over the epitaxial layer of semiconductor material;
patterning the sacrificial layer to define a dummy gate;
forming sidewall spacers on side walls of the dummy gate;
removing the dummy gate between the sidewall spacers to define a first opening; and
extending the first opening through said epitaxial layer of semiconductor material to form said opening.
24. The method of claim 21 , further comprising forming sidewall spacers on side walls of the opening and before performing said steps of annealing.
25. The method of claim 21 , wherein forming the transistor gate electrode comprises:
depositing a dielectric layer in the opening;
depositing a metal liner on the dielectric layer; and
filling said opening with a metal material.