IP Library Granted Patent US 9,538,645
Granted Patent B2
US 9,538,645 · App. 14/889,385 · Granted Jan 3, 2017

Multilayer wiring substrate

Inventors: Hisashi Kobuke (Tokyo, JP); Yousuke Futamata (Tokyo, JP); Emi Ninomiya (Tokyo, JP)
Assignee: EPCOS AG
H05K1/0306C03C12/00H05K1/0298H05K1/09H05K1/115H05K3/4629H05K3/4617H05K2201/0209H05K2201/0266
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Quick Facts
Patent No.
US 9,538,645
App. No.
14/889,385
Granted
Jan 3, 2017
Kind
B2
Abstract

A multilayer wiring substrate includes a number of insulating layers, each insulating layer including a glass ceramic. A number of internal conductor layers are formed between the insulating layers. Via conductors penetrate through the insulating layers and mutually connect the internal conductor layers in different layer locations. Surface conductor layers are formed on an outer surfaces in a lamination direction of the insulating layers. The insulating layers include outside insulating layers and inside insulating layers. A first aspect ratio representing an oblateness and sphericity of an external filler contained in the outside insulating layers is larger than a second aspect ratio representing an oblateness and sphericity of an internal filler contained in the inside insulating layers. A thermal expansion coefficient of the outside insulating layers is smaller than a thermal expansion coefficient of the inside insulating layers.

Claims (24)

1. A multilayer wiring substrate comprising:

a plurality of insulating layers, each insulating layer comprising a glass ceramic;

a plurality of internal conductor layers formed between the insulating layers;

via conductors that penetrate through the insulating layers and that mutually connect the internal conductor layers in different layer locations; and

surface conductor layers formed on an outer surfaces in a lamination direction of the insulating layers;

wherein the insulating layers within a range of a predetermined thickness from the outer surface on which the surface conductor layer is formed are defined as outside insulating layers and the insulating layers located inward of the outside insulating layers are defined as inside insulating layers;

wherein a first aspect ratio representing an oblateness and sphericity of an external filler contained in the outside insulating layers is larger than a second aspect ratio representing an oblateness and sphericity of an internal filler contained in the inside insulating layers; and

wherein a thermal expansion coefficient of the outside insulating layers is smaller than a thermal expansion coefficient of the inside insulating layers.

2. The multilayer wiring substrate as claimed in claim 1 , wherein a total thickness of the outside insulating layers is 5 to 20% of the total thickness of the multilayer wiring substrate.

3. The multilayer wiring substrate as claimed in claim 1 , wherein a via conductor ratio, defined as a value obtained by dividing the length of a longest via conductor in the direction of thickness in the multilayer wiring substrate by the total thickness of the multilayer wiring substrate, is equal to or greater than 0.4.

4. The multilayer wiring substrate as claimed in claim 1 , wherein the second aspect ratio is less than or equal to 2.

5. The multilayer wiring substrate as claimed in claim 4 , wherein the first aspect ratio is greater than or equal to 25.

6. The multilayer wiring substrate as claimed in claim 5 , wherein a mean particle size of the external filler is larger than a mean particle size of the internal filler.

7. The multilayer wiring substrate as claimed in claim 1 , wherein the first aspect ratio is greater than or equal to 25.

8. The multilayer wiring substrate as claimed in claim 1 , wherein the external filler comprises alumina.

9. The multilayer wiring substrate as claimed in claim 8 , wherein the external filler consists of alumina.

10. The multilayer wiring substrate as claimed in claim 1 , wherein a mean particle size of the external filler is larger than a mean particle size of the internal filler.

11. The multilayer wiring substrate as claimed in claim 1 , wherein a glass in the glass ceramic constituting the outside insulating layers and a glass in the glass ceramic constituting the inside insulating layers have the same composition.

12. The substrate as claimed in claim 1 , wherein a total thickness of the outside insulating layers is 5 to 20% of a total thickness of the multilayer wiring substrate; and

wherein a via conductor ratio, defined as a value obtained by dividing the length of a longest via conductor in the direction of thickness in the multilayer wiring substrate by the total thickness of the multilayer wiring substrate, is equal to or greater than 0.4.

13. The multilayer wiring substrate as claimed in claim 12 , wherein the second aspect ratio is less than or equal to 2 and wherein the first aspect ratio is greater than or equal to 25.

14. The multilayer wiring substrate as claimed in claim 13 , wherein the external filler comprises alumina.

15. The multilayer wiring substrate as claimed in claim 14 , wherein a mean particle size of the external filler is larger than a mean particle size of the internal filler.

16. The multilayer wiring substrate as claimed in claim 15 , wherein a glass in the glass ceramic constituting the outside insulating layers and a glass in the glass ceramic constituting the inside insulating layers have the same composition.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: EPCOS AG
To: SNAPTRACK, INC.
Reel/Frame 041608/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2016
From: KOBUKE, HISASHI; FUTAMATA, YOUSUKE; NINOMIYA, EMI
To: EPCOS AG
Reel/Frame 039046/0751 →
Priority Claims (1)
JP 2013-115818 · May 31, 2013 · national
Continuity (1)
Related Publication 20160088729A1 · Mar 24, 2016