IP Library Granted Patent US 10,354,586
Granted Patent B2
US 10,354,586 · App. 14/891,619 · Granted Jul 16, 2019

Image signal processing circuit, image signal processing method, and display unit with pixel degradation correction

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Quick Facts
Patent No.
US 10,354,586
App. No.
14/891,619
Granted
Jul 16, 2019
Kind
B2
Abstract

An image signal processing circuit is provided that includes a display panel, a current detection section, a modification processing section, and a correction processing section. The display panel includes a first dummy pixel that is provided outside of an effective pixel region. The current detection section detects a change in a current in the first dummy pixel. The modification processing section modifies a predetermined predicted degradation value based on an actual degradation amount of the detected current. The correction processing section corrects an image signal based on the predetermined predicted degradation value after modification. The image signal is used to drive an effective pixel.

Claims (27)

1. An image signal processing circuit comprising:

a display panel including a first dummy pixel provided outside an effective pixel region;

a current detection section configured to detect a change in a current in the first dummy pixel;

a modification processing section configured to modify a predetermined predicted degradation value, which indicates a predicted degradation per unit time, based on an actual degradation amount of the current detected by the current detection section; and

a correction processing section configured to correct an image signal, based on the predicted degradation value modified by the modification processing section, the image signal being adapted to drive an effective pixel, wherein

the current detection section includes

a detection resistor connected between an output terminal of a driver and a power supply line, the driver being configured to drive the first dummy pixel, the power supply line being configured to supply a power supply voltage to the first dummy pixel, and

a detection amplifier configured to detect a voltage value generated between both terminals of the detection resistor.

2. The image signal processing circuit according to claim 1 , wherein

the display panel has a configuration in which a power supply voltage is supplied from both sides horizontally, and

the current detection section includes a switch configured to block supply of the power supply voltage from one side of the display panel at the time of detection of the change in the current.

3. The image signal processing circuit according to claim 1 , wherein the current detection section includes a switch configured to selectively short both terminals of the detection resistor.

4. The image signal processing circuit according to claim 1 , wherein a detection pattern for detection of the change in the current is configured of a combination of always-lighting pixels operating under one or more luminance conditions, and a non-lighting pixel, and a plurality of blocks of the detection pattern are periodically provided in one line.

5. An image signal processing circuit comprising:

a display panel including a first dummy pixel provided outside an effective pixel region;

a current detection section configured to detect a change in a current in the first dummy pixel;

a modification processing section configured to modify a predetermined predicted degradation value, which indicates a predicted degradation per unit time, based on an actual degradation amount of the current detected by the current detection section; and

a correction processing section configured to correct an image signal, based on the predicted degradation value modified by the modification processing section, the image signal being adapted to drive an effective pixel, wherein,

when a light emission current of the first dummy pixel serves as a pulsed response, the current detection section detects the change in the current in synchronization with the light emission current as the pulsed response.

6. The image signal processing circuit according to claim 5 , wherein a detection pattern for detection of the change in the current is configured of a combination of always-lighting pixels operating under one or more luminance conditions, and a non-lighting pixel, and a plurality of blocks of the detection pattern are periodically provided in one line.

7. An image signal processing circuit comprising:

a display panel including a first dummy pixel provided outside an effective pixel region;

a current detection section configured to detect a change in a current in the first dummy pixel;

a modification processing section configured to modify a predetermined predicted degradation value, based on an actual degradation amount of the current detected by the current detection section; and

a correction processing section configured to correct an image signal, based on the predicted degradation value modified by the modification processing section, the image signal being adapted to drive an effective pixel,

wherein one line in a detection pattern for detection of the change in the current is divided into a plurality of pixel blocks, and is configured of one or more always-lighting pixel blocks, respective ones of the always-lighting pixel blocks operating under different luminance conditions, and a non-aging pixel block.

8. The image signal processing circuit according to claim 7 , wherein a detection pattern for detection of the change in the current is configured of a combination of always-lighting pixels operating under one or more luminance conditions, and a non-lighting pixel, and a plurality of blocks of the detection pattern are periodically provided in one line.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2015
From: MAEYAMA, KOICHI
To: JOLED INC.
Reel/Frame 037120/0731 →