IP Library Granted Patent US 9,893,088
Granted Patent B2
US 9,893,088 · App. 14/894,148 · Granted Feb 13, 2018

Thin film transistor device, method for manufacturing same and display device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,893,088
App. No.
14/894,148
Granted
Feb 13, 2018
Kind
B2
Abstract

A thin film transistor device including: a substrate; a gate electrode; an electrode pair composed of a source electrode and a drain electrode; a channel layer; and a passivation layer. The channel layer is made of an oxide semiconductor. The passivation layer includes a first layer, a second layer, and a third layer layered one on top of another in this order with the first layer closest to the substrate. The first layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride, the second layer is made of an Al compound, and the third layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride.

Claims (38)

1. A thin film transistor device comprising:

a substrate;

a gate electrode above the substrate;

a channel layer above the gate electrode;

an electrode pair on the channel layer, the electrode pair composed of a source electrode and a drain electrode that are spaced from one another;

a passivation layer extending over the gate electrode, the channel layer, and the electrode pair, the passivation layer having a hole penetrating therethrough in a thickness direction; and

an electrically-conductive layer having a portion extending along an inner wall of the passivation layer defining the hole in the passivation layer, and a portion connecting to one of the gate electrode, the source electrode, and the drain electrode at a bottom of the hole in the passivation layer,

wherein

the channel layer is made of an oxide semiconductor,

the passivation layer includes a first layer, a second layer, and a third layer layered one on top of another in this order with the first layer closest to the substrate, the first layer made of one of silicon oxide, silicon nitride, and silicon oxynitride, the second layer made of an Al compound, the third layer made of silicon nitride,

the passivation layer further includes a fourth layer on the third layer, the fourth layer made of silicon nitride, and

the fourth layer contains silicon nitride at a lower density than the third layer.

2. A thin film transistor device comprising:

a substrate;

a gate electrode above the substrate;

a channel layer above the gate electrode;

an electrode pair on the channel layer, the electrode pair composed of a source electrode and a drain electrode that are spaced from one another;

a passivation layer extending over the gate electrode, the channel layer, and the electrode pair, the passivation layer having a hole penetrating therethrough in a thickness direction; and

an electrically-conductive layer having a portion extending along an inner wall of the passivation layer defining the hole in the passivation layer, and a portion connecting to one of the gate electrode, the source electrode, and the drain electrode at a bottom of the hole in the passivation layer,

wherein

the channel layer is made of an oxide semiconductor,

the passivation layer includes a first layer, a second layer, and a third layer layered one on top of another in this order with the first layer closest to the substrate, the first layer made of one of silicon oxide, silicon nitride, and silicon oxynitride, the second layer made of an Al compound, the third layer made of silicon oxide,

the passivation layer further includes a fourth layer on the third layer, the fourth layer made of one of silicon nitride and silicon oxynitride,

at least one of the source electrode and the drain electrode contains Cu or a Cu alloy,

the fourth layer has a thickness of at least 200 nm, and

the third layer has a thickness of at least 100 nm.

3. A thin film transistor device comprising:

a substrate;

a gate electrode above the substrate;

a channel layer above the gate electrode;

an electrode pair on the channel layer, the electrode pair composed of a source electrode and a drain electrode that are spaced from one another; and

a passivation layer extending over the gate electrode, the channel layer, and the electrode pair, the passivation layer having a hole penetrating therethrough in a thickness direction,

wherein

the channel layer is made of an oxide semiconductor, and

the passivation layer includes a first layer, a second layer, and a third layer layered one on top of another in this order with the first layer closest to the substrate, the first layer made of one of silicon oxide, silicon nitride, and silicon oxynitride, the second layer made of an Al compound, the third layer made of one of silicon oxide, silicon nitride, and silicon oxynitride,

the thin film transistor device further comprises an interlayer insulating layer between the first layer and at least one of the gate electrode, the source electrode, and the drain electrode,

the interlayer insulating layer has a hole penetrating therethrough and overlapping with the hole in the passivation layer, and

the thin film transistor device further comprises an electrically-conductive layer having a portion extending along an inner wall of the interlayer insulating layer defining the hole in the interlayer insulating layer, a portion connecting to one of the gate electrode, the source electrode, and the drain electrode at a bottom of the hole in the interlayer insulating layer, and a portion residing between the interlayer insulating layer and the first layer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2015
From: SUGAWARA, YUTA
To: JOLED INC.
Reel/Frame 037142/0208 →