IP Library Granted Patent US 9,761,479
Granted Patent B2
US 9,761,479 · App. 14/902,764 · Granted Sep 12, 2017

Manufacturing method for semiconductor substrate

Inventors: Ko Imaoka (Kariya, JP); Motoki Kobayashi (Tokyo, JP); Hidetsugu Uchida (Tokyo, JP); Kuniaki Yagi (Tokyo, JP); Takamitsu Kawahara (Tokyo, JP); Naoki Hatta (Tokyo, JP); Akiyuki Minami (Tokyo, JP); Toyokazu Sakata (Tokyo, JP); Tomoatsu Makino (Tokyo, JP); Hideki Takagi (Tsukuba, JP); Yuuichi Kurashima (Tsukuba, JP)
Assignees: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI; SICOXS CORPORATION; NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
H01L21/76251H01L21/2007H01L29/1608
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Quick Facts
Patent No.
US 9,761,479
App. No.
14/902,764
Granted
Sep 12, 2017
Kind
B2
Abstract

A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.

Claims (50)

1. A manufacturing method for a semiconductor substrate, the method comprising:

mechanically polishing a surface of a support substrate to planarize the surface,

forming a first amorphous layer by destroying crystalline structures of the planarized surface of the support substrate and a second amorphous layer by destroying a crystalline structures of a surface of a single-crystalline layer of a semiconductor;

bringing the first amorphous layer and second amorphous layer into contact with each other; and

conducting a heat treatment to the support substrate and single-crystalline layer with while the first amorphous layer and the second amorphous layer being in contact with each other,

wherein a thickness of the first amorphous layer and a thickness of the second

amorphous layer is made larger as surface roughness of the support substrate and surface roughness of the single-crystalline layer becomes greater to increase fluidity of the first amorphous layer and the second amorphous layer to fill spaces formed between the first amorphous layer and the second amorphous layer.

2. The manufacturing method for a semiconductor substrate according to claim 1 , wherein

the single-crystalline layer is formed from single-crystalline SiC, and

the support substrate is formed from polycrystalline SiC.

3. The manufacturing method for a semiconductor substrate according to claim 2 , wherein the first amorphous layer and the second amorphous layer contain Si and C.

4. The manufacturing method for a semiconductor substrate according to claim 1 , wherein the forming of the first amorphous layer and the second amorphous layer includes irradiating atomic-level particles in a vacuum, and

the bringing of the first amorphous layer and the second amorphous layer into contact is carried out subsequent to the forming of the first amorphous layer and the second amorphous layer.

5. A manufacturing method for a semiconductor substrate, the method comprising:

mechanically polishing a surface of a support substrate to planarize the surface,

determining a thickness of a first amorphous layer and a thickness of a second amorphous layer depending on surface roughness of the support substrate and surface roughness of a single-crystalline layer of a semiconductor to increase fluidity of the first amorphous layer and the second amorphous layer to fill spaces formed between the first amorphous layer and the second amorphous layer;

forming the first amorphous layer having the determined thickness by destroying a crystalline structures of the planarized surface of the support substrate and the second amorphous layer having the determined thickness by destroying a crystalline structures of a surface of the single-crystalline layer of the semiconductor;

bringing the first amorphous layer and second amorphous layer into contact with each other; and

conducting a heat treatment to the support substrate and single-crystalline layer while the first amorphous layer and the second amorphous layer being in contact with each other.

6. The manufacturing method for a semiconductor substrate according to claim 5 , wherein

the single-crystalline layer is formed from single-crystalline SiC, and

the support substrate is formed from polycrystalline SiC.

7. The manufacturing method for a semiconductor substrate according to claim 6 , wherein the first amorphous layer and the second amorphous layer contain Si and C.

8. The manufacturing method for a semiconductor substrate according to claim 5 , wherein the forming of the first amorphous layer and the second amorphous layer includes irradiating atomic-level particles in a vacuum, and

the bringing of the first amorphous layer and the second amorphous layer into contact is carried out subsequent to the forming of the first amorphous layer and the second amorphous layer.

9. A manufacturing method for a semiconductor substrate, the method comprising:

mechanically polishing a surface of a support substrate to planarize the surface,

determining that: a thickness of a first amorphous layer is in a range of 1 to 20 times greater than arithmetic average roughness of the surface of the support substrate; and a thickness of a second amorphous layer is in a range of 1 to 20 times greater than arithmetic average roughness of the surface of a single-crystalline layer of a semiconductor to increase fluidity of the first amorphous layer and the second amorphous layer to fill spaces formed between the first amorphous layer and the second amorphous layer;

forming the first amorphous layer having the determined thickness by destroying a crystalline structures of the planarized surface of the support substrate; and the second amorphous layer having the determined thickness by destroying a crystalline structures of a surface of the single-crystalline layer of the semiconductor;

bringing the first amorphous layer and second amorphous layer into contact with each other; and

conducting a heat treatment to the support substrate and single-crystalline layer while the first amorphous layer and the second amorphous layer being in contact with each other.

10. The manufacturing method for a semiconductor substrate according to claim 9 , wherein

the single-crystalline layer is formed from single-crystalline SiC, and

the support substrate is formed from polycrystalline SiC.

11. The manufacturing method for a semiconductor substrate according to claim 10 , wherein the first amorphous layer and the second amorphous layer contain Si and C.

12. The manufacturing method for a semiconductor substrate according to claim 9 , wherein the forming of the first amorphous layer and the second amorphous layer includes irradiating atomic-level particles in a vacuum, and

the bringing of the first amorphous layer and the second amorphous layer into contact is carried out subsequent to the forming of the first amorphous layer and the second amorphous layer.

13. A manufacturing method for a semiconductor substrate, the method comprising:

mechanically polishing a surface of a support substrate to planarize the surface,

forming a first amorphous layer by destroying a crystalline structures of the planarized surface of the support substrate and a second amorphous layer by destroying a crystalline structures of a surface of a single-crystalline layer of a semiconductor to increase fluidity of the first amorphous layer and the second amorphous layer to fill spaces formed between the first amorphous layer and the second amorphous layer;

bringing the first amorphous layer and second amorphous layer into contact with each other; and

conducting a heat treatment to the support substrate and single-crystalline layer while the first amorphous layer and the second amorphous layer being in contact with each other,

wherein a thickness of the first amorphous layer is within a range of 1 to 2 times greater than a Peak to Valley value indicating a roughness of the surface of the support substrate, and

a thickness of the second amorphous layer is within a range of 1 to 2 times greater than a Peak to Valley value indicating a roughness of the surface of the single-crystalline layer.

14. The manufacturing method for a semiconductor substrate according to claim 13 , wherein

the single-crystalline layer is formed from single-crystalline SiC, and

the support substrate is formed from polycrystalline SiC.

15. The manufacturing method for a semiconductor substrate according to claim 14 , wherein the first amorphous layer and the second amorphous layer contain Si and C.

16. The manufacturing method for a semiconductor substrate according to claim 13 , wherein the forming of the first amorphous layer and the second amorphous layer includes irradiating atomic-level particles in a vacuum, and

the bringing of the first amorphous layer and the second amorphous layer into contact is carried out subsequent to the forming of the first amorphous layer and the second amorphous layer.

Assignments (6)
MERGER Recorded Jul 2, 2025
From: SICOXS CORPORATION
To: SUMITOMO METAL MINING CO., LTD.
Reel/Frame 071586/0447 →
CHANGE OF ADDRESS FOR ASSIGNEE - NEW ADDRESS Recorded Dec 16, 2021
From: SICOXS CORPORATION
To: SICOXS CORPORATION
Reel/Frame 058520/0306 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR EXECUTION DATE PREVIOUSLY RECORDED ON REEL 043722 FRAME 0029. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF THE ASSIGNOR'S INTEREST. Recorded Oct 6, 2017
From: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
To: SICOXS CORPORATION
Reel/Frame 044143/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2017
From: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI; SICOXS CORPORATION
To: SICOXS CORPORATION
Reel/Frame 043722/0029 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2016
From: IMAOKA, KO; KOBAYASHI, MOTOKI; UCHIDA, HIDETSUGU; YAGI, KUNIAKI; KAWAHARA, TAKAMITSU; HATTA, NAOKI; MINAMI, AKIYUKI; SAKATA, TOYOKAZU; MAKINO, TOMOATSU; TAKAGI, HIDEKI; KURASHIMA, YUUICHI
To: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI; SICOXS CORPORATION; NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
Reel/Frame 037853/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2016
From: IMAOKA, KO; KOBAYASHI, MOTOKI; UCHIDA, HIDETSUGU; YAGI, KUNIAKI; KAWAHARA, TAKAMITSU; HATTA, NAOKI; MINAMI, AKIYUKI; SAKATA, TOYOKAZU; MAKINO, TOMOATSU; TAKAGI, HIDEKI; KURASHIMA, YUUICHI
To: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI; SICOXS CORPORATION; NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
Reel/Frame 037426/0091 →
Priority Claims (1)
JP 2013-142151 · Jul 5, 2013 · national
Continuity (1)
Related Publication 20160204023A1 · Jul 14, 2016