Chip power supply method and chip
View Patent ↗The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.
1. A chip power supply method, wherein a configuration memory array provides a configuration voltage to a negative channel metal oxide semiconductor (NMOS) transmission gate via an NMOS drain of the configuration memory, and a low-dropout (LDO) circuit supplies power to the configuration memory and the chip, the method comprising:
determining that a working state of the chip has switched from a first state to a second state, wherein the first state and the second state are each one of an initial mode, a program mode, or a user mode;
when the working state changes, adjusting, according to the working state of the chip, a configuration bit provided to the LDO circuit; and
adjusting, based on the adjusted configuration bit, an output voltage of the LDO circuit output to the configuration memory and to the chip.
2. The method according to claim 1 , wherein,
the first state is the initial mode, and the output voltage of the LDO circuit is a first voltage;
the second state is the program mode; and
the adjusting an output voltage of the LDO circuit comprises changing the output voltage of the LDO circuit from the first voltage to a second output voltage.
3. The method according to claim 1 , wherein,
the first state is the program mode, and the output voltage of the LDO circuit is a second voltage;
the second state is the user mode; and
the adjusting an output voltage of the LDO circuit comprises changing the output voltage of the LDO circuit from the second voltage to a third output voltage.
4. The method according to claim 1 , wherein the adjusting a configuration bit to adjust an output voltage of the LDO circuit specifically comprises:
adjusting, by means of adjusting the configuration bit, a resistance value of a variable resistor of the LDO circuit, to control the output voltage of the LDO circuit.
5. A chip comprising:
a negative channel metal oxide semiconductor (NMOS) transmission gate;
a configuration memory array configured to provide a configuration voltage to the NMOS transmission gate via an NMOS drain of the configuration memory; and
a low-dropout (LDO) circuit configured to supply power to the configuration memory and the chip,
wherein, when the chip determines that a working state of the chip switches from a first state to a second state, wherein the first state and the second state are each one of an initial mode, a program mode, or a user mode, the chip adjusts, according to the working state of the chip, a configuration bit provided to the LDO circuit, and the LDO adjusts, according to the configuration bit obtained after the adjusting, an output voltage of the LDO circuit output to the configuration memory and to the chip.
6. The chip according to claim 5 , wherein,
the first state is the initial mode, and the output voltage of the LDO circuit is a first voltage;
the second state is the program mode; and
the adjusting an output voltage of the LDO circuit comprises changing the output voltage of the LDO circuit from the first voltage to a second output voltage.
7. The chip according to claim 5 , wherein,
the first state is the program mode, and the output voltage of the LDO circuit is a second voltage;
the second state is the user mode; and
the adjusting an output voltage of the LDO circuit comprises changing the output voltage of the LDO circuit from the second voltage to a third output voltage.
8. The chip according to claim 5 , wherein the chip is A Field Programmable Gate Array (FPGA) chip.
9. The chip according to claim 5 , wherein switchover of the working state is implemented by means of chip configuration.