IP Library Granted Patent US 9,729,144
Granted Patent B2
US 9,729,144 · App. 14/908,735 · Granted Aug 8, 2017

Isolated uni-polar transistor gate drive

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Quick Facts
Patent No.
US 9,729,144
App. No.
14/908,735
Granted
Aug 8, 2017
Kind
B2
Abstract

According to one aspect, a transistor gate drive comprises a first input configured to be coupled to a DC voltage source, a second input configured to receive a control signal, a third input configured to couple to a ground connection, a transformer, a first switch configured to couple the first input to a first end of a primary winding of the transformer in response to receipt of the control signal, and to decouple the first input from the first end of the primary winding in response to the receipt of the control signal, a second switch configured to couple a second end of the primary winding to the third input in response to receipt of the control signal, and to decouple the second end of the primary winding from the third input in response to the receipt of the control signal.

Claims (42)

1. A transistor gate drive comprising:

a first input configured to be coupled to a DC voltage source;

a second input configured to receive a control signal;

a third input configured to couple to a ground connection;

a transformer having a primary winding and at least one secondary winding, the primary winding having a first end and a second end;

a first switch having a control input and configured to couple the first input to the first end of the primary winding in response to receipt of the control signal having a first level, and to decouple the first input from the first end of the primary winding in response to the receipt of the control signal having a second level;

a second switch having a control input and configured to couple the second end of the primary winding to the third input in response to receipt of the control signal having the first level, and to decouple the second end of the primary winding from the third input in response to the receipt of the control signal having the second level;

a Pulse Width Modulation (PWM) controller coupled to the first switch and the second switch and configured to generate the control signal;

a first diode coupled between the first switch and the first end of the primary winding and further coupled to the third input; and

a second diode coupled to the first input and further coupled between the second switch and the second end of the primary winding.

2. The transistor gate drive of claim 1 , wherein the first diode and the second diode are configured to provide a path for a reset of the primary winding.

3. The transistor gate drive of claim 1 , wherein the first switch includes a control pin coupled to the second input, a collector coupled to the first input and an emitter coupled between the first diode and the primary winding of the transformer.

4. The transistor gate drive of claim 1 , wherein the second switch is a MOSFET having a drain coupled between the primary winding and the second diode and a source coupled to the third input.

5. The transistor gate drive of claim 1 , wherein the primary winding and the secondary winding have a same polarity.

6. The transistor gate drive of claim 5 , further comprising at least one secondary circuit coupled to the at least one secondary winding of the transformer and having an output configured to drive a control pin of a transistor based on a level of the control signal.

7. The transistor gate drive of claim 6 , wherein the at least one secondary circuit comprises:

a turn-off switch; and

a turn-on diode, wherein the turn-off switch and the turn-on diode are coupled in parallel with the at least one secondary winding of the transformer, and wherein a junction point between the turn-on diode and the turn-off switch are coupled to the output of the at least one secondary circuit.

8. The transistor gate drive of claim 7 , further comprising a pull-down resistor coupled between the output of the at least one secondary circuit and an output ground connection.

9. The transistor gate drive of claim 1 , wherein the PWM controller is configured to generate the control signal having a duty cycle of 50% or less.

10. The transistor gate drive of claim 9 , wherein the duty cycle is a variable duty cycle based on input signal provided to the PWM controller.

11. A method of operating a transistor gate drive circuit, the method comprising:

receiving a DC input voltage at a first input of the transistor gate drive circuit;

receiving, in a turn-on mode, a control signal at a second input of the transistor gate drive circuit from a Pulse Width Modulation (PWM) controller, the control signal having a first level and a duty cycle;

coupling, responsive to receipt of the control signal having the first level, the first input to a first end of a primary winding of a transformer;

coupling, responsive to receipt of the control signal having the first level, a second end of the primary winding of the transformer to a ground connection;

receiving, in a turn-off mode, the control signal at the second input of the transistor gate drive circuit, the control signal having a second level; and

discharging, in response to the receipt of the control signal having the second level, the transformer.

12. The method of claim 11 , further comprising:

inducing, in the turn-on mode, a current in at least one secondary winding of the transformer; and

using the current, driving at least one primary switch of at least one output circuit to turn on.

13. The method of claim 11 , further comprising:

decoupling, responsive to receipt of the control signal having the second level, the first input from the first end of the primary winding of the transformer;

decoupling, responsive to receipt of the control signal having the second level, the second end of the primary winding of the transformer from the ground connection; and

resetting the primary winding of the transformer through a first diode and a second diode.

14. The method of claim 13 , wherein resetting includes limiting a voltage across the first switch and the second switch.

15. The method of claim 13 , further comprising:

driving, in response to resetting the primary winding, a turn-off switch to turn on;

coupling, in response to the turn-off switch turning on, a control pin of at least one primary switch of at least one output circuit to a second ground connection; and

driving the at least one primary switch to turn off.

16. The method of claim 11 , further comprising:

changing the duty cycle of the control signal from a first duty to a second duty cycle.

Assignments (4)
NOTICE OF ASSIGNMENT OF INTELLECTUAL PROPERTY SECURITY AGREEMENTS Recorded Mar 14, 2025
From: THE GOVERNOR AND COMPANY OF THE BANK OF IRELAND (RETIRING AGENT)
To: NXT CAPITAL, LLC (SUCCESSOR AGENT)
Reel/Frame 070520/0931 →
INTELLECTUAL PROPERTY ASSIGNMENT Recorded Dec 4, 2018
From: SCHNEIDER ELECTRIC SOLAR INVERTERS USA, INC.
To: XANTREX LLC
Reel/Frame 047716/0381 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 30, 2018
From: XANTREX LLC
To: THE GOVERNOR AND COMPANY OF THE BANK OF IRELAND, AS COLLATERAL AGENT
Reel/Frame 048174/0107 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2016
From: ESMAEILI, MORTEZA
To: SCHNEIDER ELECTRIC SOLAR INVERTERS USA, INC.
Reel/Frame 037619/0818 →