Method and system for interference cancellation of data channel

1. A method for interference cancellation of a data channel, comprising:

performing bit-level channel recording comprising bit collection on received transport block data, and then performing channel estimation on the recoded data and multiplexed antenna data of a data channel to obtain channel estimation data;

performing data channel reconstruction on the recoded data with a Reconstruction Unit (RU) as a unit by virtue of the channel estimation data; and

subtracting obtained reconstruction data from the antenna data to implement interference cancellation.

2. The method according to claim 1 , further comprising: transmitting different frequency offset parameters to antennae forming an antenna pair.

3. The method according to claim 1 , wherein the data channel reconstruction is implemented by: preferably selecting a path with larger energy for reconstruction according to path energy.

4. The method according to claim 1 , wherein the bit-level channel recoding comprises:

coding the received transport block data to obtain Turbo coded data in a Turbo coding manner; executing primary First-In First-Out (FIFO) caching on the Turbo coded data; performing rate matching on the primary cached data, and then executing secondary FIFO caching; performing bit collection on the secondary cached data, and then executing tertiary FIFO caching; and performing secondary interleaving processing on the tertiary cached data, and outputting the recoded data and interleaving addresses.

5. The method according to claim 4 , wherein secondary interleaving processing comprises:

performing row-column transform on an interleaving pattern at first, and calculating interleaving addresses where current coded data should be stored;

outputting the bit-collected data, and writing the bit-collected data into a Random Access Memory (RAM) according to the calculated storage addresses; and

when the interleaved data is required, sequentially reading the data stored in the RAM to implement interleaving.

6. The method according to claim 1 , wherein performing channel estimation on the recoded data and the multiplexed antenna data of the data channel comprises:

receiving a data packet parameter, and requesting for antenna data after the data packet parameter is received; performing antenna data chip-level processing on the obtained antenna data, and then executing antenna data symbol-level processing; outputting the processed antenna data of the data channel and the processed antenna data of a control channel in parallel; performing real-time data channel filtering processing on the antenna data of the data channel;

after a complete data packet is received, starting amplitude offset estimation of the control channel; and after the amplitude offset of the control channel is calculated, reading a data channel filtering result, performing bit slicing processing to obtain a channel estimation value of the data channel, and multiplying the obtained channel estimation value by the amplitude offset of the control channel to obtain a channel estimation value of the control channel.

7. The method according to claim 1 , when a reconstruction conflict occurs during data channel reconstruction, the method further comprising:

after performing filtered data branching processing on filtered data, outputting current user data and previous user data in two paths, a time delay interval between adjacent two pieces of user data being equal to a length of a data conflict window;

performing accumulation, overflow and bit slicing processing operation on the current user data, the previous user data and original reconstruction data to obtain reconstruction operation result data; and

storing the reconstruction operation result data, each user occupying an address field space and reconstruction RAM addresses being progressively increase in sequence according to system time.

8. The method according to claim 7 , wherein read-write control over the reconstruction RAM comprises:

reading corresponding original reconstruction data from a corresponding location of the reconstruction RAM according to system time corresponding to current reconstruction data and a user offset; and performing reconstruction operation on the data read from the reconstruction RAM, and transmitting an updated reconstruction data to the corresponding location of the reconstruction RAM to update the original reconstruction data.

9. A system for interference cancellation of a data channel, comprising:

a processor; and

a memory configured to store instructions executable by the processor;

wherein the processor is configured to:

perform bit-level channel recoding comprising bit collection on received transport block data to obtain recoded data;

perform channel, estimation on the recoded data and multiplexed antenna data of a data channel to obtain channel estimation data; and

perform data channel reconstruction on the recoded data with a Reconstruction Unit (RU) as a unit by virtue of the channel estimation data, and subtract the obtained reconstruction data from the antenna data to implement interference cancellation.

10. The system according to claim 9 , wherein the processor is further configured to transmit different frequency offset parameters to antennae forming an antenna pair.

11. The system according to claim 9 , wherein when the processor is configured to perform the data channel reconstruction, the processor is configured to preferably selects a path with larger energy for reconstruction according to path energy.

12. The system according to claim 9 , wherein when the processor is configured to perform bit-level channel recoding on the received transport block data to obtain recoded data, the processor is configured to:

code the received transport block data to obtain Turbo coded data in a Turbo coding manner;

cache the Turbo coded data, cache rate-matched data and cache bit-collected data in multiple FIFO caches;

match each bit and a transmission channel to confirm whether to repeat or punch;

collect coded bit data; and

perform secondary interleaving processing on received FIFO cached data, and output the recoded data and interleaving addresses.

13. The system according to claim 12 , wherein when the processor is configured to perform secondary interleaving processing on the received FIFO cached data, and output the recoded data and interleaving addresses, the processor is configured to perform row-column transform on an interleaving pattern at first, pre-calculate interleaving addresses where current coded data should be stored, output the bit-collected data, simultaneously write the bit-collected data into a Random Access Memory (RAM) according to the calculated storage addresses, and sequentially read the RAM to implement interleaving when the interleaved data is required.

14. The system according to claim 9 , wherein when the processor is configured to perform channel estimation on the recoded data and multiplexed antenna data of the data channel to obtain the channel estimation data, the processor is configured to:

receive a data packet parameter, request for antenna data after the data packet parameter is received, perform antenna data chip-level processing on the antenna data to obtain processed antenna data;

perform symbol-level processing on the processed antenna data to obtain processed antenna data of the data channel and the processed antenna data of a control channel in parallel;

perform real-time data channel filtering processing on the antenna data of the data channel; and

after a complete data packet is received, start amplitude offset estimation of the control channel, start executing amplitude offset estimation on the control channel, read a data channel filtering result after an amplitude offset of the control channel is calculated, perform bit slicing processing to obtain a channel estimation value of the data channel, and multiply the obtained channel estimation value by the amplitude offset of the control channel to obtain a channel estimation value of the control channel.

15. The system according to claim 9 , wherein when the processor is configured to perform the data channel reconstruction, the processor is configured to:

receive filtered data, and output current user data and previous user data in two paths, a time delay interval between adjacent two pieces of user data being equal to a length of a data conflict window;

execute reconstruction operation, and specifically perform accumulation, overflow and bit slicing processing operation on the current user data, the previous user data and original reconstruction data to obtain reconstruction operation result data; and

store the reconstruction operation result data in a reconstruction data storage, each user occupying an address field space and addresses of a reconstruction RAM being progressively increase in sequence according to system time.

16. The system according to claim 15 , wherein the processor is configured to perform read-write control on the reconstruction RAM;

read-write control over the reconstruction RAM comprises: reading corresponding original reconstruction data from a corresponding location of the reconstruction RAM according to system time corresponding to current reconstruction data and a user offset; and then performing reconstruction operation on the data read from the reconstruction RAM, and transmitting an updated reconstruction data to the corresponding location of the reconstruction RAM to update the old reconstruction result data.