Chip Scale Package
A novel semiconductor chip scale package encapsulates a semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.
1 . A semiconductor device package, comprising:
a semiconductor chip having a device side with metallic contact bumps thereon, a non-device side opposite the device side, and four edges;
a first layer of mold compound covering the four edges and the device side of the chip;
a second layer of mold compound covering the non-device side of the chip; and
the first layer of mold compound joining the second layer of mold compound at a plane that is coplanar to the non-device side of the chip.
2 . The semiconductor device package of claim 1 , in which a top portion of the contact bumps on the device side of the semiconductor chip protrude from the first layer of mold compound.
3 . The semiconductor device package of claim 2 , in which the protruding portion of the contact bumps is covered with a metallic film containing gold.
4 . The semiconductor device package of claim 3 , in which the contact bums nickel.
5 . The semiconductor device package of claim 1 , in which the first layer of mold compound contains filler particles.
6 . The semiconductor device package of claim 5 , further comprising partially ground filler particles near the plane where the first layer and the second layer of mold compound meet.
7 . The semiconductor of claim 6 , in which the partially ground filler particles are embedded in the first layer of mold compound.
8 . The semiconductor of claim 7 , in which the partially ground filler particles are not embedded in the second mold compound.
9 . A process of fabricating a semiconductor device package, comprising:
providing a semiconductor wafer with chips, each chip having a device side, a non-device side and four edges;
covering with a first mold compound the device side and the four edges of the semiconductor chip;
removing a portion of the semiconductor chip from the non-device side and a portion of the first mold compound to create a plane; and
covering the plane with a second mold compound.
10 . The process of claim 9 , further comprising forming trenches around the chips.
11 . The process of claim 10 in which the step of covering with first mold compound comprising filling the trenches with the first mold compound.
12 . The process of claim 11 , in which the removing step comprises removing the first mold compound from a portion of the trenches.
13 . The process of claim 12 , in which the removing step comprising a mechanical grinding process.
14 . The process of claim 13 , in which the grinding process leaves partially ground filler particles near the plane.
15 . The process of claim 9 , further comprising forming contact bumps on the device side of the chips.
16 . The process of claim 15 , in which the covering with a first mold compound step comprising uncovering a top portion of the contact bumps from the first mold compound.
17 . The process of claim 16 , further comprising coating the uncovered portion of the contact bumps with a noble metal, including gold.