Correlation detector
A correlation detector comprises an input unit configured to receive a plurality of parallel data streams of discrete events. The correlation detector further comprises a memory array having a plurality of resistive memory elements. At least one resistive memory element is allocated to each of the parallel data streams. Furthermore, a programming array is provided comprising a plurality of programming elements. At least one programming element is allocated to each resistive memory element for applying a programming signal to the respective memory element. The correlation detector comprises further a control unit that is configured to control the programming signals as a function of a co-arrival characteristic of the discrete events. A correlation unit is configured to detect correlations between the received data streams based on resistance changes of the resistive memory elements.
1. A correlation detector comprising:
an input unit configured to receive a plurality of parallel data streams of discrete events;
a memory array comprising a plurality of resistive memory elements, wherein at least one of the resistive memory elements is allocated to each of the data streams;
a programming array comprising a plurality of programming elements, wherein at least one of the programming elements is allocated to each resistive memory element for applying a programming signal to the respective memory element;
a control unit configured to control the programming signals as a function of a co-arrival characteristic of the discrete events;
a correlation unit configured to detect correlations between the data streams based on resistance changes of the resistive memory elements.
2. A detector as claimed in claim 1 , wherein the function of the co-arrival characteristic is function of the number of co-arrivals of the discrete events at any instant in time.
3. A detector as claimed in claim 1 , wherein the function of the co-arrival characteristic is a function of the number of co-arrivals of the discrete events within a predefined interval of time.
4. A detector as claimed in claim 1 , wherein the control unit is configured to control one of a voltage, a current and the duration of the application of power applied to the resistive memory elements.
5. A detector as claimed in claim 1 , wherein the correlation unit is configured to measure a distribution of the resistance and/or conductance of the resistive memory elements.
6. A detector as claimed in claim 1 , wherein the correlation unit is configured to measure a time at which the resistance and/or conductance of the resistive memory elements diverges.
7. A detector as claimed in claim 1 , comprising one or more inverter units for altering one or more of the plurality of parallel data streams such that an arrival of a discrete event is altered to a non-arrival and a non-arrival of a discrete event is altered to an arrival.
8. A detector as claimed in claim 1 , comprising one or more delay units for delaying one or more of the plurality of parallel data streams with a predefined delay.
9. A detector as claimed in claim 1 , comprising:
a first set of resistive memory elements; and
a second set of resistive memory elements;
wherein the control unit is configured to control the programming signal applied to the resistive memory elements of the first set as a first function of the co-arrival characteristic of the discrete events and to control the programming signal applied to the resistive memory elements of the second set as a second function of the co-arrival characteristic of the discrete events.
10. A detector as claimed in claim 1 , wherein the resistive memory elements are one of Phase change memory (PCM) elements, Conductive bridge resistive memory elements, Metal-oxide resistive random access memory (RRAM) elements and Magneto-resistive random access memory (MRAM) elements.
11. A detector as claimed in claim 1 , wherein the programming unit comprises transistors as programming elements arranged in series to the resistive memory elements and wherein the control unit is configured to control the gate voltage of the transistors.
12. A detector as claimed in claim 1 , wherein the resistive memory elements are Phase change memory cells and wherein the control unit is configured to:
apply a Reset-pulse to the PCM cells in order to bring the PCM-cells in the amorphous state;
apply current pulses to the PCM cells that heat the PCM cells above the crystallization temperature, thereby lowering the resistance of the PCM cells.