Semiconductor integrated circuit device comprising MISFETs in SOI and bulk subtrate regions
The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
1. A semiconductor integrated circuit device comprising:
a semiconductor substrate having a first MISFET formation region, a second MISFET formation region, and a device isolation region located between the first MISFET formation region and the second MISFET formation region;
an insulator layer formed in the first MISFET formation region, and formed on a surface of the semiconductor substrate;
a semiconductor layer formed in the first MISFET formation region, and formed on the insulator layer;
a first gate electrode formed in the first MISFET formation region, and formed on a surface of the semiconductor layer via a first gate insulative film;
a second gate electrode formed in the second MISFET formation region, and formed on the surface of the semiconductor substrate via a second gate insulative film;
a silicide film formed on the second gate electrode; and
an interlayer insulative film formed over the surface of the semiconductor substrate such that a surface of the first gate electrode is exposed from the interlayer insulative film, and such that a surface of the silicide film is covered with the interlayer insulative film,
wherein, in a cross-section view, a length from the surface of the semiconductor layer to the surface of the first gate electrode, which is along a thickness of the first gate electrode, is greater than a length from the surface of the semiconductor substrate to the surface of the silicide film, which is along a thickness of the second gate electrode.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein a gate length of the second gate electrode is greater than a gate length of the first gate electrode.
3. The semiconductor integrated circuit device according to claim 1 ,
wherein the first gate electrode is comprised of a metal film, and
wherein the second gate electrode is comprised of a polycrystalline silicon film.
4. The semiconductor integrated circuit device according to claim 1 ,
wherein a side surface of the first gate electrode is covered with a first sidewall spacer,
wherein a side surface of the second gate electrode is covered with a second sidewall spacer, and
wherein, in cross-section view, a length from the surface of the semiconductor layer to a surface of the first sidewall spacer, which is along the thickness of the first gate electrode, is greater than a length from the surface of the semiconductor substrate to a surface of the second sidewall spacer, which is along the thickness of the second gate electrode.
5. The semiconductor integrated circuit device according to claim 4 ,
wherein a thickness of the insulator layer is less than or equal to 15 nm, and
wherein a thickness of the semiconductor layer is less than or equal to 20 nm.
6. The semiconductor integrated circuit device according to claim 5 ,
wherein, in the first MISFET formation region, first elevated regions having an impurity therein are formed on the surface of the semiconductor layer at both sides of the first gate electrode via the first sidewall spacer.