Systems and methods for compaction based flash memory data recovery
View Patent ↗Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing data to and accessing data from a flash memory.
1. A system for accessing a flash memory device, the system comprising:
a data read circuit operable to compare voltages read from a set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers;
a compaction based partial decoder circuit operable to compact a subset of the M groups of N binary values to yield a compacted output, wherein the compacted output is represented in fewer bits than a number of bits used to represent the subset of the M groups of N binary values; and
a first data decoding circuit operable to generate at least one soft data value based upon the compacted output, wherein the soft data value corresponds to an element of a given codeword represented by the M groups of N binary values.
2. The system of claim 1 , wherein the subset of the M groups of N binary values is a first subset of the M groups of N binary values, wherein the compacted output is a first compacted output, and wherein the compaction based partial decoder circuit is further operable to:
repeatedly compact additional subsets of the M groups of N binary values to yield corresponding additional compacted outputs; and
wherein the first decoder circuit is further operable to generate at least one additional soft data value based upon each of the respective additional compacted outputs.
3. The system of claim 2 , the system further comprising:
a second data decoding circuit operable to apply a data decoding algorithm to the given codeword to yield a decoded output.
4. The system of claim 3 , wherein the given codeword is a low density parity check codeword, and wherein the second data decoding circuit is a low density parity check decoding circuit.
5. The system of claim 1 , wherein N is three, wherein the subset of the M groups of N binary values is one group of the N binary values, and wherein the compacted output is a ternary number represented by two bits.
6. The system of claim 1 , wherein N is three, wherein the subset of the M groups of N binary values is three groups of the N binary values, and wherein the compacted output is a ternary number represented by five bits.
7. The system of claim 1 , wherein N is three, wherein the subset of the M groups of N binary values is five groups of the N binary values, and wherein the compacted output is ternary number represented by eight bits.
8. The system of claim 1 , wherein the given codeword is a first codeword, wherein the at least one soft data value is a first soft data value, wherein the binary output set is a first binary output set; wherein the data read circuit is further operable to compare voltages read from the set of M groups of N flash memory cells with a second threshold value to yield a second binary output set; and wherein the first data decoding circuit is further operable to:
generate at least a second soft data value directly from the second binary output set, wherein the second soft data value corresponds to an element of a second codeword represented by the M groups of N binary values.
9. The system of claim 8 , wherein the first data decoding circuit comprises:
a first look-up table including soft data values corresponding to respective values of the compacted output; and
a second look-up table including soft data values corresponding to respective values of the N binary values.
10. The system of claim 1 , wherein the set of M groups of N binary values is a first set of M groups of N binary values, wherein the given codeword is a first codeword, wherein the at least one soft data value is a first soft data value, wherein the binary output set is a first binary output set; wherein the data read circuit is further operable to compare voltages read from the set of M groups of N flash memory cells with a second threshold value to yield a second binary output set, and wherein the compaction based partial decoder circuit is further operable to:
compact a subset of a second set of M groups of N binary values to yield a second compacted output, wherein the second compacted output is represented in fewer bits than a number of bits used to represent the subset of the second set of M groups of N binary values; and
wherein the first data decoding circuit is further operable to:
generate at least a second soft data value directly from the second binary output set, wherein the second soft data value corresponds to an element of a second codeword represented by the M groups of N binary values.
11. The system of claim 10 , wherein the first data decoding circuit comprises:
a first look-up table including soft data values corresponding to respective values of the first compacted output; and
a second look-up table including soft data values corresponding to respective values of the first compacted output.
12. The system of claim 1 , wherein M is the number of elements in the given codeword.
13. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.
14. A method for accessing data from a flash memory device, the method comprising:
accessing a set of M groups of N flash memory cells to yield M groups of N voltages, and wherein M and N are integers;
using a read circuit to compare the M groups of N voltages with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values;
compacting a subset of the M groups of N binary values to yield a compacted output, wherein the compacted output is represented in fewer bits a number of bits used to represent the subset of the M groups of N binary values; and
generating at least one soft data value based upon the compacted output, wherein the soft data value corresponds to an element of a given codeword represented by the M groups of N binary values.
15. The method of claim 14 , wherein N is three, wherein the subset of the M groups of N binary values is one group of the N binary values, and wherein the compacted output is a ternary number represented by two bits.
16. The method of claim 14 , wherein N is three, wherein the subset of the M groups of N binary values is three groups of the N binary values, and wherein the compacted output is a ternary number represented by five bits.
17. The method of claim 14 , wherein N is three, wherein the subset of the M groups of N binary values is five groups of the N binary values, and wherein the compacted output is ternary number represented by eight bits.
18. The method of claim 14 , wherein the subset of the M groups of N binary values is a first subset of the M groups of N binary values, wherein the compacted output is a first compacted output, and wherein the method further comprises:
repeatedly compacting additional subsets of the M groups of N binary values to yield corresponding additional compacted outputs;
generating at least one additional soft data value based upon each of the respective additional compacted outputs; and
applying a data decoding algorithm to the given codeword to yield a decoded output.
19. A flash memory system, the system comprising:
a set of M groups of N flash memory cells;
a write circuit operable to encode a data input to a M groups of N voltages, and to program the M groups of N flash memory cells with the M groups of N voltages;
a data read circuit operable to compare voltages read from the set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers;
a compaction based partial decoder circuit operable to compact a subset of the M groups of N binary values to yield a compacted output, wherein the compacted output is represented in fewer bits than a number of bits used to represent the subset of the M groups of N binary values; and
a first data decoding circuit operable to generate at least one soft data value based upon the compacted output, wherein the soft data value corresponds to an element of a given codeword represented by the M groups of N binary values.
20. The flash memory system of claim 19 , wherein the subset of the M groups of N binary values is a first subset of the M groups of N binary values, wherein the compacted output is a first compacted output, and wherein the compaction based partial decoder circuit is further operable to:
repeatedly compact additional subsets of the M groups of N binary values to yield corresponding additional compacted outputs;
wherein the first decoder circuit is further operable to generate at least one additional soft data value based upon each of the respective additional compacted outputs; and
wherein the system further includes a second data decoding circuit operable to apply a data decoding algorithm to the given codeword to yield a decoded output.