ESD PROTECTION AND LIMITER CIRCUIT
Electrostatic discharge protection circuits and methods of operation are described. An ESD circuit may include two circuit branches, each including a transistor, that are arranged to shunt voltage and current between two circuit terminals responsive to an over-voltage condition between the two terminals. A turn-on voltage of each transistor may be set by series-connected diodes.
1 . An electrostatic discharge (ESD) protection circuit comprising:
a first terminal;
a second terminal;
a first diode stack connected between the first terminal and a control terminal of a first transistor;
a first current-carrying terminal of the first transistor coupled to the first terminal; and
a second current-carrying terminal of the first transistor coupled to the second terminal.
2 . The ESD protection circuit of claim 1 , further comprising:
a first shunt diode having a cathode connected to the first current-carrying terminal of the first transistor and an anode connected to the first terminal; and
a first base diode having a cathode connected to a control terminal of the first transistor and an anode connected to the first diode stack.
3 . The ESD protection circuit of claim 1 , further comprising:
a second diode stack connected between the second terminal and a control terminal of a second transistor;
a first current-carrying terminal of the second transistor coupled to the second terminal; and
a second current-carrying terminal of the second transistor coupled to the first terminal.
4 . The ESD protection circuit of claim 3 , further comprising:
a first shunt diode having a cathode connected to the first current-carrying terminal of the first transistor and an anode connected to the first terminal;
a first base diode having a cathode connected to a control terminal of the first transistor and an anode connected to the first diode stack;
a second shunt diode having a cathode connected to the first current-carrying terminal of the second transistor and an anode connected to the second terminal; and
a second base diode having a cathode connected to a control terminal of the second transistor and an anode connected to the second diode stack.
5 . The ESD protection circuit of claim 4 , having a capacitance between the first terminal and second terminal less than 2 pF.
6 . The ESD protection circuit of claim 5 , wherein the capacitance is less than 2 pF over a range of frequencies between approximately 0.1 GHz and approximately 12 GHz.
7 . The ESD protection circuit of claim 4 , formed on a semiconductor die within an area measuring less than 100 μm×100 μm.
8 . The ESD protection circuit of claim 4 , wherein the anode of the first base diode and anode of the second base diode are connected to a same node that is between the first diode stack and the second diode stack.
9 . The ESD protection circuit of claim 4 , wherein the first transistor and second transistor are heterojunction bipolar transistors.
10 . The ESD protection circuit of claim 9 , wherein the heterojunction bipolar transistors comprise gallium arsenide.
11 . The ESD protection circuit of claim 4 , wherein the first terminal is connected to an input terminal of a gallium-nitride amplifier circuit.
12 . The ESD protection circuit of claim 4 , wherein the first shunt diode and the second shunt diode are Schottky diodes.
13 . An electrostatic discharge protection circuit comprising:
a first terminal;
a second terminal;
a first circuit branch connected between the first terminal and the second terminal, wherein the first circuit branch includes a first shunt diode connected between a first current-carrying terminal of a first transistor and the first terminal;
a second circuit branch connected between the first terminal and the second terminal, wherein the second circuit branch includes a second shunt diode connected between a first current-carrying terminal of a second transistor and the second terminal, wherein the protection circuit is configured to turn on the first transistor when a voltage between the first terminal and second terminal exceeds a positive value and the protection circuit is configured to turn on the second transistor when a voltage between the first terminal and second terminal falls below a negative value.
14 . The ESD protection circuit of claim 13 , wherein an absolute value of the negative value is approximately equal to the positive value.
15 . The ESD protection circuit of claim 13 , wherein the first terminal is connected to a radio-frequency input terminal of a gallium-nitride amplifier circuit.
16 . The ESD protection circuit of claim 13 , wherein the first transistor and second transistor are heterojunction bipolar transistors.
17 . The ESD protection circuit of claim 16 , wherein the heterojunction bipolar transistors comprise gallium arsenide.
18 . The ESD protection circuit of claim 13 , further comprising:
a first base diode having a cathode connected to a control terminal of the first transistor; and
a first diode stack connected between the first terminal and an anode of the first base diode, wherein the positive value is determined at least in part by the first base diode and first diode stack.
19 . The ESD protection circuit of claim 18 , further comprising:
a second base diode having a cathode connected to a control terminal of the second transistor; and
a second diode stack connected between the second terminal and an anode of the second base diode, wherein the negative value is determined at least in part by the second base diode and second diode stack.
20 . The ESD protection circuit of claim 19 , having a capacitance between the first terminal and second terminal of less than 2 pF.
21 . The ESD protection circuit of claim 20 , wherein the capacitance is less than 2 pF over a range of frequencies between approximately 0.1 GHz and approximately 12 GHz.
22 . The ESD protection circuit of claim 19 , formed on a semiconductor die within an area measuring less than 100 μm×100 μm.
23 . A method of protecting a circuit, the method comprising:
receiving a voltage at a first terminal;
applying the voltage across a first diode stack and a first base diode that are connected in series with a control terminal of a first transistor;
turning on the first transistor if the voltage exceeds a first value; and
shunting current through current-carrying terminals of the first transistor and a first shunt diode between the first terminal and a second terminal.
24 . The method of claim 23 , further comprising:
applying the voltage across a second diode stack and a second base diode that are connected in series with a control terminal of a second transistor;
turning on the second transistor if the voltage is less than a second value; and
shunting current through current-carrying terminals of the second transistor and a second shunt diode between the first terminal and the second terminal.
25 . The method of claim 24 , wherein an absolute value of the second value is approximately equal to the first value.
26 . The method of claim 24 , further comprising shunting the current from a radio-frequency input of a gallium-nitride amplifier.
27 . The method of claim 26 , further comprising receiving the voltage as a time varying signal that varies at one or more frequencies between approximately 0.1 GHz and approximately 12 GHz.